IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 43

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

4
registers in the device. The microprocessor interface supports Serial
mode only.
When CLKE is asserted low, data on SDO will be clocked out on the ris-
Microprocessor Interface
IDT82V3255
The microprocessor interface provides access to read and write the
In a read operation, the active edge of SCLK is selected by CLKE.
MICROPROCESSOR INTERFACE
SCLK
SDI
SDO
SDO
CS
SCLK
SDI
CS
t
t
su2
su1
R/W
R/W
t
Figure 15. Serial Read Timing Diagram (CLKE Asserted High)
Figure 14. Serial Read Timing Diagram (CLKE Asserted Low)
h1
A0
A0
A1
A1
A2
High-Z
A2
High-Z
t
pw1
A3
A3
t
pw2
A4
A4
A5
A5
43
A6
A6
ing edge of SCLK. When CLKE is asserted high, data on SDO will be
clocked out on the falling edge of SCLK.
of SCLK.
t
d1
In a write operation, data on SDI will be clocked in on the rising edge
t
d1
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
t
d2
t
h2
t
D7
t
d2
D7
h2
December 3, 2008
WAN PLL