IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 53

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

T4_T0_REG_SEL_CNFG - T0 / T4 Registers Selection Configuration
PHASE_ALARM_TIME_OUT_CNFG - Phase Lock Alarm Time-Out Configuration
Programming Information
IDT82V3255
Address: 08H
Type: Read / Write
Default Value: 00110010
Address: 07H
Type: Read / Write
Default Value: XXX0XXXX
MULTI_FACTO
7 - 6
5 - 0
7 - 5
3 - 0
Bit
Bit
4
R1
7
7
-
TIME_OUT_VALUE[5:0]
MULTI_FACTOR[1:0]
T4_T0_SEL
Name
MULTI_FACTO
-
-
Name
R0
6
6
-
Reserved.
A part of the registers are shared by T0 and T4 paths. These registers are addressed 27H, 28H, 2AH, 4EH, 4FH, 5AH, 5BH, 62H
~ 64H, 68H and 69H. This bit determines whether the register configuration is available for T0 or T4 path.
0: T0 path (default).
1: T4 path.
Reserved.
TIME_OUT_VA
These bits determine a factor which has a relationship with a period in seconds. A phase lock alarm will be raised if the T0
selected input clock is not locked in T0 DPLL within this period. If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, the
phase lock alarm will be cleared after this period (starting from when the alarm is raised). Refer to the description of the
TIME_OUT_VALUE[5:0] bits (b5~0, 08H).
00: 2 (default)
01: 4
10: 8
11: 16
These bits represent an unsigned integer. If the value in these bits is multiplied by the value in the MULTI_FACTOR[1:0]
bits (b7~6, 08H), a period in seconds will be gotten.
A phase lock alarm will be raised if the T0 selected input clock is not locked in T0 DPLL within this period. If the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, the phase lock alarm will be cleared after this period (starting from when the
alarm is raised).
LUE5
5
5
-
TIME_OUT_VA
T4_T0_SEL
LUE4
4
4
53
TIME_OUT_VA
LUE3
3
3
-
Description
Description
TIME_OUT_VA
LUE2
2
2
-
TIME_OUT_VA
LUE1
1
1
-
December 3, 2008
TIME_OUT_VAL
UE0
0
0
-
WAN PLL