IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 10

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

DESCRIPTION
chronous Equipment Timing Source for Stratum 3, SMC, 4E and 4
clocks in SONET / SDH equipments, DWDM and Wireless base station,
such as GSM, 3G, DSL concentrator, Router and Access Network appli-
cations.
clock from STM-N or OC-n, PDH network synchronization timing and
external synchronization reference timing.
sists of T0 and T4 paths. The T0 path is a high quality and highly config-
urable path to provide system clock for node timing synchronization
within a SONET / SDH network. The T4 path is simpler and less config-
urable for equipment synchronization. The T4 path locks independently
from the T0 path or locks to the T0 path.
each for DPLL locking. Both the T0 and T4 paths support three primary
operating modes: Free-Run, Locked and Holdover. In Free-Run mode,
the DPLL refers to the master clock. In Locked mode, the DPLL locks to
Description
IDT82V3255
The IDT82V3255 is an integrated, single-chip solution for the Syn-
The device supports three types of input clock sources: recovered
Based on ITU-T G.783 and Telcordia GR-253-CORE, the device con-
An input clock is automatically or manually selected for T0 and T4
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the selected input clock. In Holdover mode, the DPLL resorts to the fre-
quency data acquired in Locked mode. Whatever the operating mode is,
the DPLL gives a stable performance without being affected by operat-
ing conditions or silicon process variations.
device will be in a better jitter/wander performance.
Hz in 11 steps and damping factors: 1.2 to 20 in 5 steps. Different set-
tings cover all SONET / SDH clock synchronization requirements.
cations. The master clock is used as a reference clock for all the internal
circuits in the device. It can be calibrated within ±741 ppm.
cessor interface. The device supports Serial microprocessor interface
mode only.
If the DPLL outputs are processed by T0/T4 APLL, the outputs of the
The device provides programmable DPLL bandwidths: 0.1 Hz to 560
A high stable input is required for the master clock in different appli-
All the read/write registers are accessed through a serial micropro-
The device can be used typically in Line Card application.
December 3, 2008
WAN PLL