IDT82V3255TFG IDT, Integrated Device Technology Inc, IDT82V3255TFG Datasheet - Page 9

• Manufacturer Part Number: IDT82V3255TFG
• Description: IC PLL WAN SMC STRATUM 3 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3255TFG

• Input: CMOS, LVDS, PECL
• Output: CMOS, LVDS, PECL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3255TFG

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
 2008 Integrated Device Technology, Inc.
FEATURES
HIGHLIGHTS
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MAIN FEATURES
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The first single PLL chip:
• Features 0.1 Hz to 560 Hz bandwidth
• Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/
• Provides node clocks for Cellular and WLL base-station (GSM
• Provides clocks for DSL access concentrators (DSLAM), espe-
Provides an integrated single-chip solution for Synchronous Equip-
ment Timing Source, including Stratum 3, SMC, 4E and 4 clocks
Employs DPLL and APLL to feature excellent jitter performance
and minimize the number of the external components
Integrates T0 DPLL and T4 DPLL; T4 DPLL locks independently or
locks to T0 DPLL
Supports Forced or Automatic operating mode switch controlled by
an internal state machine; the primary operating modes are Free-
Run, Locked and Holdover
Supports programmable DPLL bandwidth (0.1 Hz to 560 Hz in 11
steps) and damping factor (1.2 to 20 in 5 steps)
Supports 1.1X10
ppm instantaneous holdover accuracy
Supports PBO to minimize phase transients on T0 DPLL output to
be no more than 0.61 ns
Supports phase absorption when phase-time changes on T0
selected input clock are greater than a programmable limit over an
interval of less than 0.1 seconds
Supports programmable input-to-output phase offset adjustment
Limits the phase and frequency offset of the outputs
Supports manual and automatic selected input clock switch
Option I) jitter generation requirements
and 3G networks)
cially for Japan TCM-ISDN network timing based ADSL equip-
ments
-5
ppm absolute holdover accuracy and 4.4X10
WAN PLL
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OTHER FEATURES
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APPLICATIONS
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Supports automatic hitless selected input clock switch on clock fail-
ure
Supports three types of input clock sources: recovered clock from
STM-N or OC-n, PDH network synchronization timing and external
synchronization reference timing
Provides three 2 kHz, 4 kHz or 8 kHz frame sync input signals, and
a 2 kHz and an 8 kHz frame sync output signals
Provides 5 input clocks whose frequency cover from 2 kHz to
622.08 MHz
Provides 2 output clocks whose frequency cover from 1 Hz to
622.08 MHz
Provides output clocks for BITS, GPS, 3G, GSM, etc.
Supports PECL/LVDS and CMOS input/output technologies
Supports master clock calibration
Supports Line Card application
Meets Telcordia GR-1244-CORE, GR-253-CORE, ITU-T G.812,
ITU-T G.813 and ITU-T G.783 criteria
Serial microprocessor interface mode
IEEE 1149.1 JTAG Boundary Scan
Single 3.3 V operation with 5 V tolerant CMOS I/Os
64-pin TQFP package, Green package options available
BITS / SSU
SMC / SEC (SONET / SDH)
DWDM cross-connect and transmission equipments
Central Office Timing Source and Distribution
Core and access IP switches / routers
Gigabit and Terabit IP switches / routers
IP and ATM core switches and access equipments
Cellular and WLL base-station node clocks
Broadband and multi-service access equipments
Any other telecom equipments that need synchronous equipment
system timing
IDT82V3255
December 3, 2008
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