ADV7341BSTZ Analog Devices Inc, ADV7341BSTZ Datasheet - Page 98

• Manufacturer Part Number: ADV7341BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7341BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 12b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7340/ADV7341
Table 74. 10-Bit NTSC Square Pixel YCrCb In (EAV/SAV),
CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x88
0x8C
0x8D
0x8E
0x8F
Table 75. 30-Bit NTSC Square Pixel RGB In, CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x87
0x88
0x8A
0x8C
0x8D
0x8E
0x8F
Table 76. 10-Bit 625i YCrCb In (EAV/SAV), YPrPb and
CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x88
Setting
0x02
0x1C
0x00
0x10
0xDB
0x10
0x55
0x55
0x55
0x25
Setting
0x02
0x1C
0x00
0x10
0xDB
0x80
0x10
0x0C
0x55
0x55
0x55
0x25
Setting
0x02
0xFC
0x00
0x11
0xC1
0x10
Description
Software reset
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled. Square pixel mode enabled.
10-bit YCbCr input enabled.
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output in
NTSC square pixel mode (24.5454 MHz
input clock).
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. CVBS/Y-C (S-Video) out.
SSAF PrPb filter enabled. Active video
edge control enabled. Pedestal
enabled. Square pixel mode enabled.
RGB input enabled.
30-bit RGB input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Subcarrier frequency register values
for CVBS and/or S-Video (Y-C) output in
NTSC square pixel mode (24.5454 MHz
input clock).
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
10-bit input enabled.
Rev. A | Page 98 of 108
Table 77. 10-Bit 625i YCrCb In, YPrPb and CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x88
0x8A
Table 78. 10-Bit 625i YCrCb In (EAV/SAV), RGB and
CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x02
0x80
0x82
0x88
Table 79. 10-Bit 625i YCrCb In, RGB and CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x02
0x80
0x82
0x88
0x8A
0x02
0xFC
0x00
0x11
0xC1
0x10
0x0C
0x02
0xFC
0x00
0x10
0x11
0xC1
0x10
0x02
0xFC
0x00
0x10
0x11
0xC1
0x10
0x0C
Setting
Setting
Setting
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
10-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
10-bit input enabled.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
PAL standard. SSAF luma filter enabled.
1.3 MHz chroma filter enabled.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled.
10-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.