ADV7341BSTZ Analog Devices Inc, ADV7341BSTZ Datasheet - Page 104

• Manufacturer Part Number: ADV7341BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7341BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 12b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7340/ADV7341
HIGH DEFINITION
Table 113. HD Configuration Scripts
Input Format
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
720p at 60 Hz/59.94 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1080i at 30 Hz/29.97 Hz
1
Table 114. 10-Bit 720p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
SDR = single data rate. DDR = dual data rate.
Setting
0x02
0x1C
0x20
0x2C
0x01
0x6C
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
720p at 60 Hz/59.94 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
Pixel data valid. 4× oversampling.
10-bit input enabled.
Input Data Width
10-bit DDR
10-bit DDR
10-bit DDR
10-bit DDR
20-bit SDR
20-bit SDR
20-bit SDR
20-bit SDR
30-bit SDR
30-bit SDR
30-bit SDR
30-bit SDR
30-bit SDR
10-bit DDR
10-bit DDR
10-bit DDR
10-bit DDR
20-bit SDR
20-bit SDR
20-bit SDR
20-bit SDR
30-bit SDR
30-bit SDR
30-bit SDR
30-bit SDR
30-bit SDR
1
Synchronization Format
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
HSYNC / VSYNC
Rev. A | Page 104 of 108
Table 115. 10-Bit 720p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
YCrCb
YCrCb
Input Color Space
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
0x02
0x1C
0x20
0x28
0x01
0x6C
Setting
Output Color Space
YPrPb
YPrPb
RGB
RGB
YPrPb
YPrPb
RGB
RGB
YPrPb
YPrPb
RGB
RGB
RGB
YPrPb
YPrPb
RGB
RGB
YPrPb
YPrPb
RGB
RGB
YPrPb
YPrPb
RGB
RGB
RGB
Description
Software reset.
All DACs enabled. PLL enabled (4×).
HD-DDR input mode. Luma data
clocked on falling edge of CLKIN.
720p at 60 Hz/59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output
levels.
Pixel data valid. 4× oversampling.
10-bit input enabled.
Table Number
Table 114
Table 115
Table 116
Table 117
Table 118
Table 119
Table 120
Table 121
Table 122
Table 123
Table 124
Table 125
Table 126
Table 127
Table 128
Table 129
Table 130
Table 131
Table 132
Table 133
Table 134
Table 135
Table 136
Table 137
Table 138
Table 139