ADV7341BSTZ Analog Devices Inc, ADV7341BSTZ Datasheet - Page 96

• Manufacturer Part Number: ADV7341BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7341BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 12b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7340/ADV7341
CONFIGURATION SCRIPTS
The scripts listed in the following pages can be used to configure the ADV7340/ ADV7341 for basic operation. Certain features are
enabled by default. If required for a specific application, additional features can be enabled. Table 65 lists the scripts available for SD
modes of operation. Similarly, Table 86 and Table 113 list the scripts available for ED and HD modes of operation, respectively. For all
scripts, only the necessary register writes are included. All other registers are assumed to have their default values.
STANDARD DEFINITION
Table 65. SD Configuration Scripts
Input Format
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
525i (NTSC)
NTSC Sq. Pixel
NTSC Sq. Pixel
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
625i (PAL)
PAL Sq. Pixel
PAL Sq. Pixel
1
Table 66. 10-Bit 525i YCrCb In (EAV/SAV), YPrPb and
CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x88
SDR = single data rate.
Setting
0x02
0xFC
0x00
0x10
0xC9
0x10
Input Data Width
10-bit SDR
10-bit SDR
10-bit SDR
10-bit SDR
20-bit SDR
20-bit SDR
30-bit SDR
30-bit SDR
10-bit SDR
30-bit SDR
10-bit SDR
10-bit SDR
10-bit SDR
10-bit SDR
20-bit SDR
20-bit SDR
30-bit SDR
30-bit SDR
10-bit SDR
30-bit SDR
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
10-bit input enabled.
1
Synchronization Format
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
HSYNC / VSYNC
HSYNC / VSYNC
HSYNC / VSYNC
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
HSYNC / VSYNC
HSYNC / VSYNC
HSYNC / VSYNC
HSYNC / VSYNC
EAV/SAV
HSYNC / VSYNC
Rev. A | Page 96 of 108
Input Color Space
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
RGB
YCrCb
RGB
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
YCrCb
RGB
RGB
YCrCb
RGB
Table 67. 10-Bit 525i YCrCb In, YPrPb and CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x88
0x8A
0x02
0xFC
0x00
0x10
0xC9
0x10
0x0C
Setting
Output Color Space
YPrPb and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
YPrPb and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
CVBS/Y-C (S-Video)
YPrPb and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
YPrPb and CVBS/Y-C
YPrPb and CVBS/Y-C
RGB and CVBS/Y-C
CVBS/Y-C (S-Video)
CVBS/Y-C (S-Video)
RGB and CVBS/Y-C
RGB and CVBS/Y-C
CVBS/Y-C (S-Video)
RGB and CVBS/Y-C
RGB and CVBS/Y-C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
10-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table Number
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
Table 73
Table 74
Table 75
Table 76
Table 77
Table 78
Table 79
Table 80
Table 81
Table 82
Table 83
Table 84
Table 85