ADV7341BSTZ Analog Devices Inc, ADV7341BSTZ Datasheet - Page 69

• Manufacturer Part Number: ADV7341BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7341BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 12b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL
For synchronization purposes, the ADV7340/ADV7341 are able to accept either time codes embedded in the input pixel data or external
synchronization signals provided on the S_HSYNC , S_VSYNC , P_HSYNC , P_VSYNC , and P_BLANK pins (see
possible to output synchronization signals on the
Table 55. Timing Synchronization Signal Input Options
Signal
SD HSYNC In
SD VSYNC In
ED/HD HSYNC In
ED/HD VSYNC In
ED/HD BLANK In
1
Table 56. Timing Synchronization Signal Output Options
Signal
SD HSYNC Out
SD VSYNC Out
ED/HD HSYNC Out
ED/HD VSYNC Out
1
Table 57. HSYNC Output Control
ED/HD Input Sync
Format (Subaddress
0x30, Bit 2)
X
X
0
1
X
1
2
SD and ED/HD timing sync. Outputs must also be disabled (Subaddress 0x02[7:6] = 00).
ED/HD timing sync. Outputs must also be disabled (Subaddress 0x02, Bit 7 = 0).
In all ED/HD standards where there is an HSYNC output, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.
X = don’t care.
ED/HD HSYNC
Control
(Subaddress
0x34, Bit 1)
X
X
0
0
1
Pin
S_HSYNC
S_VSYNC
P_HSYNC
P_VSYNC
P_BLANK
Pin
S_HSYNC
S_VSYNC
S_HSYNC
S_VSYNC
1, 2
ED/HD Sync
Output Enable
(Subaddress
0x02, Bit 7)
0
1
1
1
0
Condition
SD slave timing mode (1, 2, or 3) selected (Subaddress 0x8A[2:0]).
SD Slave timing mode (1, 2, or 3) selected (Subaddress 0x8A[2:0]).
ED/HD timing sync; inputs enabled (Subaddress 0x30, Bit 2 = 0).
ED/HD timing sync; inputs enabled (Subaddress 0x30, Bit 2 = 0).
Condition
SD timing sync; outputs enabled (Subaddress 0x02, Bit 6 = 1).
SD timing sync; outputs enabled (Subaddress 0x02, Bit 6 = 1).
ED/HD timing sync; outputs enabled (Subaddress 0x02, Bit 7 = 1).
ED/HD timing sync; outputs enabled (Subaddress 0x02, Bit 7 = 1).
S_HSYNC and S_VSYNC pins (see
Rev. A | Page 69 of 108
SD Sync Output
Enable
(Subaddress
0x02, Bit 6)
0
1
X
X
X
Signal on S_HSYNC Pin
Three-state.
Pipelined SD HSYNC.
Pipelined ED/HD HSYNC.
Pipelined ED/HD HSYNC based on
the AV Code H bit.
Pipelined ED/HD HSYNC based on
the horizontal counter.
Table 56
to
Table 58
1
1
).
1
1
ADV7340/ADV7341
Table 55
Duration
N/A.
See the
section.
As per HSYNC timing.
Same as line blanking
interval.
Same as embedded
HSYNC.
). It is also
SD Timing