ADV7341BSTZ Analog Devices Inc, ADV7341BSTZ Datasheet - Page 101

• Manufacturer Part Number: ADV7341BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7341BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 12b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Table 89. 10-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
Table 90. 10-Bit 525p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
Table 91. 20-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
Table 92. 20-Bit 525p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
Setting
0x02
0x1C
0x20
0x10
0x04
0x01
0x6C
Setting
0x02
0x1C
0x20
0x10
0x00
0x01
0x6C
Setting
0x02
0x1C
0x10
0x04
0x01
0x6C
Setting
0x02
0x1C
0x10
0x00
0x01
0x6C
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. HSYNC/VSYNC
synchronization. EIA-770.2 output
levels.
Pixel data valid.
10-bit input enabled.
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
525p at 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled (10 × 2 = 20-bit).
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
525p at 59.94 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled (10 × 2 = 20-bit).
Rev. A | Page 101 of 108
Table 93. 20-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
Table 94. 20-Bit 525p YCrCb In, RGB Out
Subaddress
0x17
0x00
0x01
0x02
0x30
0x31
0x33
Table 95. 30-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
Table 96. 30-Bit 525p YCrCb In, YPrPb Out
Subaddress
0x17
0x00
0x01
0x30
0x31
0x33
Setting
0x02
0x1C
0x10
0x10
0x04
0x01
0x6C
Setting
0x02
0x1C
0x10
0x10
0x00
0x01
0x6C
Setting
0x02
0x1C
0x10
0x04
0x01
0x2C
Setting
0x02
0x1C
0x10
0x00
0x01
0x2C
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled (10 × 2 = 20-bit).
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
525p at 59.94 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
10-bit input enabled (10 × 2 = 20-bit).
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
525p at 59.94 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data. 10-bit input enabled
(10 × 3 = 30-bit).
Description
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
525p at 59.94 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
4:4:4 input data. 10-bit input enabled
(10 × 3 = 30-bit).
ADV7340/ADV7341