ADV7341BSTZ Analog Devices Inc, ADV7341BSTZ Datasheet - Page 42

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ADV7341BSTZ

Manufacturer Part Number
ADV7341BSTZ
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADV7341BSTZ

Number Of Dac's
6
Adc/dac Resolution
12b
Screening Level
Industrial
Package Type
LQFP
Pin Count
64
Lead Free Status / RoHS Status
Compliant

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ADV7340/ADV7341
SR7 to
SR0
0x88
0x89
1
Table 30. Register 0x8A to Register 0x98
SR7 to
SR0
0x8A
When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
Register
SD Mode
Register 7
SD Mode
Register 8
Register
SD Timing Register 0
Bit Description
Reserved.
SD noninterlaced mode
SD double buffering
SD input format
SD digital noise reduction
SD gamma correction enable
SD gamma correction curve select
SD undershoot limiter
Reserved
SD black burst output on DAC luma
SD chroma delay
Reserved
Bit Description
SD slave/master mode
SD timing mode
Reserved
SD luma delay
SD minimum luma value
SD timing reset
Rev. A | Page 42 of 108
7
0
1
7
0
1
0
6
0
1
0
6
0
1
5
0
1
0
0
1
1
Bit Number
5
0
0
1
1
4
0
0
1
1
0
1
0
1
Bit Number
4
0
1
0
1
3
1
0
1
1
0
0
3
1
2
0
1
0
1
1
0
1
0
0
1
1
2
0
0
1
1
0
0
0
1
0
1
1
1
0
1
0
Register Setting
Disabled.
Enabled.
Disabled.
Enabled.
8-bit YCbCr input.
16-bit YCbCr input.
10-bit YCbCr input/16-/24-/30-bit RGB.
20-bit YCbCr input.
Disabled.
Enabled.
Disabled.
Enabled.
Gamma Correction Curve A.
Gamma Correction Curve B.
Disabled.
−11 IRE.
−6 IRE.
−1.5 IRE.
0 must be written to this bit.
Disabled.
Enabled.
Disabled.
Four clock cycles.
Eight clock cycles.
Reserved.
0 must be written to these bits.
0
0
1
Register Setting
Slave mode.
Master mode.
Mode 0.
Mode 1.
Mode 2.
Mode 3.
No delay.
Two clock cycles.
Four clock cycles.
Six clock cycles.
−40 IRE.
−7.5 IRE.
Normal operation.
Freezes the counters; this bit
must be set back to zero in
order to reset the counters
and resume operation.
Reset
Value
0x00
0x00
Reset
Value
0x08

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