ADV7341BSTZ Analog Devices Inc, ADV7341BSTZ Datasheet - Page 97

• Manufacturer Part Number: ADV7341BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7341BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 12b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Table 68. 10-Bit 525i YCrCb In (EAV/SAV), RGB and
CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x02
0x80
0x82
0x88
Table 69. 10-Bit 525i YCrCb In, RGB and CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x02
0x80
0x82
0x88
0x8A
Table 70. 20-Bit 525i YCrCb In, YPrPb and CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x88
0x8A
Setting
0x02
0xFC
0x00
0x10
0x10
0xC9
0x10
Setting
0x02
0xFC
0x00
0x10
0x10
0xC9
0x10
0x0C
Setting
0x02
0xFC
0x00
0x10
0xC9
0x18
0x0C
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
10-bit input enabled.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
10-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
20-bit input enabled.
Timing Mode 2 (slave). HSYNC / VSYNC
synchronization.
Rev. A | Page 97 of 108
Table 71. 20-Bit 525i YCrCb In, RGB and CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x02
0x80
0x82
0x88
0x8A
Table 72. 30-Bit 525i RGB In, YPrPb and CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x80
0x82
0x87
0x88
0x8A
Table 73. 30-Bit 525i RGB In, RGB and CVBS/Y-C Out
Subaddress
0x17
0x00
0x01
0x02
0x80
0x82
0x87
0x88
0x8A
Setting
0x02
0xFC
0x00
0x10
0x10
0xC9
0x18
0x0C
Setting
0x02
0xFC
0x00
0x10
0xC9
0x80
0x10
0x0C
Setting
0x02
0xFC
0x00
0x10
0x10
0xC9
0x80
0x10
0x0C
Description
Software reset
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
20-bit input enabled.
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
RGB input enabled.
10-bit input enabled (10 × 3 = 30-bit).
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Description
Software reset.
All DACs enabled. PLL enabled (16×).
SD input mode.
RGB output enabled. RGB output sync
enabled.
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
RGB input enabled.
10-bit input enabled (10 × 3 = 30-bit).
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
ADV7340/ADV7341