ADV7341BSTZ Analog Devices Inc, ADV7341BSTZ Datasheet - Page 35

• Manufacturer Part Number: ADV7341BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7341BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 12b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Table 22. Register 0x31 to Register 0x33
SR7 to
SR0
0x31
0x32
0x33
Register
ED/HD Mode
Register 2
ED/HD Mode
Register 3
ED/HD Mode
Register 4
Bit Description
ED/HD pixel data valid
Reserved
ED/HD test pattern enable
ED/HD test pattern hatch/field
ED/HD VBI open
ED/HD undershoot limiter
ED/HD sharpness filter
ED/HD Y delay with respect to the falling
edge of HSYNC
ED/HD color delay with respect to the
falling edge of HSYNC
ED/HD CGMS
ED/HD CGMS CRC
ED/HD Cr/Cb sequence
Reserved
ED/HD input format
Sinc compensation filter on DAC 1, DAC 2,
DAC 3
Reserved
ED/HD chroma SSAF
ED/HD chroma input
ED/HD double buffering
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7
0
1
0
1
0
1
6
0
0
1
1
0
1
0
1
5
0
1
0
1
0
0
0
0
1
0
1
Bit Number
4
0
1
0
0
1
1
0
0
3
0
1
0
1
0
1
0
0
1
2
0
1
0
0
0
0
1
1
0
1
0
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
Register Setting
Pixel data valid off.
Pixel data valid on.
ED/HD test pattern off.
ED/HD test pattern on.
Hatch.
Field/frame.
Disabled.
Enabled.
Disabled.
−11 IRE.
−6 IRE.
−1.5 IRE.
Disabled.
Enabled.
0 clock cycles.
One clock cycle.
Two clock cycles.
Three clock cycles.
Four clock cycles.
0 clock cycles.
One clock cycle.
Two clock cycles.
Three clock cycles.
Four clock cycles.
Disabled.
Enabled.
Disabled.
Enabled.
Cb after falling edge of HSYNC.
Cr after falling edge of HSYNC.
0 must be written to this bit.
8-bit input.
10-bit input.
Disabled.
Enabled.
0 must be written to this bit.
Disabled.
Enabled.
4:4:4.
4:2:2.
Disabled.
Enabled.
ADV7340/ADV7341
Reset
Value
0x00
0x00
0x68