ADV7341BSTZ Analog Devices Inc, ADV7341BSTZ Datasheet - Page 56

• Manufacturer Part Number: ADV7341BSTZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7341BSTZ

• Number Of Dac's: 6
• Adc/dac Resolution: 12b
• Screening Level: Industrial
• Package Type: LQFP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7340/ADV7341
In SD Timing Mode 0 (slave option), if VBI is enabled, the
blanking bit in the EAV/SAV code is overwritten. It is possible
to use VBI in this timing mode as well.
If CGMS is enabled and VBI is disabled, the CGMS data is,
nevertheless, available at the output.
SD SUBCARRIER FREQUENCY CONTROL
Subaddress 0x8C to Subaddress 0x8F
The ADV7340/ADV7341 is able to generate the color subcarrier
used in CVBS and S-Video (Y-C) outputs from the input pixel
clock. Four 8-bit registers are used to set up the subcarrier
frequency. The value of these registers is calculated using
where the sum is rounded to the nearest integer. For example, in
NTSC mode
where:
Subcarrier Register Value = 569408543d = 0×21F07C1F
SD F
SD F
SD F
SD F
Programming the F
The subcarrier frequency register value is divided into four F
registers, as shown in the previous example. The four subcarrier
frequency registers must be updated sequentially, starting with
Subcarrier Frequency Register 0 and ending with Subcarrier
Frequency Register 3. The subcarrier frequency updates only
after the last subcarrier frequency register byte is received by
the ADV7340/ADV7341. The SD input standard autodetection
feature must be disabled.
Typical F
Table 43 outlines the values that should be written to the
subcarrier frequency registers for NTSC and PAL B/D/G/H/I.
SC
SC
SC
SC
Subcarrier
Subcarrier
Number
Number
Register 0: 0x1F
Register 1: 0x7C
Register 2: 0xF0
Register 3: 0x21
SC
Values
of
of
Frequency
Register
subcarrier
27
MHz
SC
Value
clk
Register
periods
cycles
=
⎛
⎜
⎝
227
1716
=
in
in
5 .
one
one
⎞
⎟
⎠
×
video
video
2
32
=
line
line
569408543
×
2
32
Rev. A | Page 56 of 108
SC
Table 43. Typical F
Subaddress
0x8C
0x8D
0x8E
0x8F
SD NONINTERLACED MODE
Subaddress 0x88, Bit 1
The ADV7340/ADV7341 support an SD noninterlaced mode.
Using this mode, progressive inputs at twice the frame rate of
NTSC and PAL (240p/59.94 Hz and 288p/50 Hz, respectively)
can be input into the ADV7340/ADV7341. The SD noninter-
laced mode can be enabled using Subaddress 0x88, Bit 1.
A 27 MHz clock signal must be provided on the CLKIN_A pin.
Embedded EAV/SAV timing codes or external horizontal and
vertical synchronization signals provided on the S_HSYNC and
S_VSYNC pins can be used to synchronize the input pixel data.
All input configurations, output configurations, and features
available in NTSC and PAL modes are available in SD noninter-
laced mode. For 240p/59.94 Hz input, the ADV7340/ADV7341
should be configured for NTSC operation, and Subaddress
0x88, Bit 1 should be set to 1.
For 288p/50 Hz input, the ADV7340/ADV7341 should be con-
figured for PAL operation,and Subaddress 0x88, Bit 1 should be
set to 1.
SD SQUARE PIXEL MODE
Subaddress 0x82, Bit 4
The ADV7340/ADV7341 support an SD square pixel mode
(Subaddress 0x82, Bit 4). For NTSC operation, an input clock of
24.5454 MHz is required. The active resolution is 640 × 480. For
PAL operation, an input clock of 29.5 MHz is required. The
active resolution is 768 × 576.
For CVBS and S-Video (Y-C) outputs, the SD subcarrier
frequency registers must be updated to reflect the input clock
frequency used in SD square pixel mode. The SD input standard
autodetection feature must be disabled in SD square pixel
mode. In square pixel mode, the timing diagrams shown in
Figure 63 and Figure 64 apply.
Description
F
F
F
F
SC
SC
SC
SC
SC
0
1
2
3
Values
NTSC
0x1F
0x7C
0xF0
0x21
PAL B/D/G/H/I
0xCB
0x8A
0x09
0x2A