SAA7105E/V1/G NXP Semiconductors, SAA7105E/V1/G Datasheet - Page 71

• Manufacturer Part Number: SAA7105E/V1/G
• Description: Video ICs PC-DENC
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant
• Other names: SAA7105E/V1/G,557

Philips Semiconductors
13. Test information
SAA7104E_SAA7105E_2
Product data sheet
13.1.1 Initialization of boundary scan circuit
13.1.2 Device identification codes
13.1 Boundary scan test
The SAA7104E; SAA7105E has built-in logic and 5 dedicated pins to support boundary
scan testing which allows board testing without special hardware (nails). The SAA7104E;
SAA7105E follows the ‘IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan
Architecture’ set by the Joint Test Action Group (JTAG) chaired by Philips.
The 5 special pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST),
Test Data Input (TDI) and Test Data Output (TDO).
The Boundary Scan Test (BST) functions BYPASS, EXTEST, SAMPLE, CLAMP and
IDCODE are all supported; see
found in the specification ‘IEEE Std. 1149.1’ . A file containing the detailed Boundary Scan
Description Language (BSDL) of the SAA7104E; SAA7105E is available on request.
Table 114: BST instructions supported by the SAA7104E; SAA7105E
The Test Access Port (TAP) controller of an IC should be in the reset state
(TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces
the instruction register into a functional instruction such as IDCODE or BYPASS.
To solve the power-up reset, the standard specifies that the TAP controller will be forced
asynchronously to the TEST_LOGIC_RESET state by setting the TRST pin LOW.
A device identification register is specified in ‘IEEE Std. 1149.1b-1994’ . It is a 32-bit
register which contains fields for the specification of the IC manufacturer, the IC part
number and the IC version number. Its biggest advantage is the possibility to check for the
correct ICs mounted after production and to determine the version number of the ICs
during field service.
When the IDCODE instruction is loaded into the BST instruction register, the identification
register will be connected between pins TDI and TDO of the IC. The identification register
will load a component specific code during the CAPTURE_DATA_REGISTER state of the
TAP controller, this code can subsequently be shifted out. At board level this code can be
Instruction
BYPASS
EXTEST
SAMPLE
CLAMP
IDCODE
Description
This mandatory instruction provides a minimum length serial path (1 bit) between
TDI and TDO when no test operation of the component is required.
This mandatory instruction allows testing of off-chip circuitry and board level
interconnections.
This mandatory instruction can be used to take a sample of the inputs during
normal operation of the component. It can also be used to preload data values into
the latched outputs of the boundary scan register.
This optional instruction is useful for testing when not all ICs have BST. This
instruction addresses the bypass register while the boundary scan register is in
external test mode.
This optional instruction will provide information on the components manufacturer,
part number and version number.
Rev. 02 — 23 December 2005
Table
114. Details about the JTAG BST-TEST can be
SAA7104E; SAA7105E
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Digital video encoder
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