SAA7105E/V1/G NXP Semiconductors, SAA7105E/V1/G Datasheet - Page 45

• Manufacturer Part Number: SAA7105E/V1/G
• Description: Video ICs PC-DENC
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant
• Other names: SAA7105E/V1/G,557

Philips Semiconductors
SAA7104E_SAA7105E_2
Product data sheet
Table 49:
Legend: * = default value after reset and minimum value.
Table 50:
Table 51:
Legend: * = default value after reset.
Table 52:
Legend: * = default value after reset.
Table 53:
Legend: * = default value after reset.
Bit
7 to 4 -
3 to 0 TTXHD[3:0]
Bit
7 to 3 CSYNCA[4:0] R/W
2 to 0 -
Bit
7 to 0 TTXOVS[7:0] R/W
Bit
7 to 0 TTXOVE[7:0] R/W
Bit
7 to 0 TTXEVS[7:0] R/W
Symbol
Symbol
Symbol
Symbol
Symbol
TTX request horizontal delay register, subaddress 74h, bit description
CSYNC advance register, subaddress 75h, bit description
TTX odd request vertical start register, subaddress 76h, bit description
TTX odd request vertical end register, subaddress 77h, bit description
TTX even request vertical start register, subaddress 78h, bit description
Access Value Description
Access Value Description
Access Value Description
Access Value Description
R/W
R/W
Rev. 02 — 23 December 2005
Access Value Description
R/W
04h*
05h*
05h*
06h*
16h*
10h*
0h
2h*
-
000
with TTXEVS8 (see
signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in
even field, line = (TTXEVS + 4) for M-systems and
line = (TTXEVS + 1) for other systems
if strapped to PAL
if strapped to NTSC
with TTXOVS8 (see
signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in
odd field, line = (TTXOVS + 4) for M-systems and
line = (TTXOVS + 1) for other systems
if strapped to PAL
if strapped to NTSC
with TTXOVE8 (see
signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in
odd field, line = (TTXOVE + 3) for M-systems and
line = TTXOVE for other systems
if strapped to PAL
if strapped to NTSC
must be programmed with logic 0 to ensure compatibility
to future enhancements
indicates the delay in clock cycles between rising edge of
TTXRQ output signal on pin TTXRQ_XCLKO2
(CLK2EN = 0) and valid data at pin TTX_SRES
advanced composite sync against RGB output from
0 XTAL clocks to 31 XTAL clocks
must be programmed with logic 0 to ensure compatibility
to future enhancements
SAA7104E; SAA7105E
Table
Table
Table
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
57) first line of occurrence of
57) first line of occurrence of
57) last line of occurrence of
Digital video encoder
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