SAA7105E/V1/G NXP Semiconductors, SAA7105E/V1/G Datasheet - Page 20

• Manufacturer Part Number: SAA7105E/V1/G
• Description: Video ICs PC-DENC
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant
• Other names: SAA7105E/V1/G,557

Philips Semiconductors
SAA7104E_SAA7105E_2
Product data sheet
7.18 I
7.19 Power-down modes
7.20 Programming the SAA7104E; SAA7105E
The I
and 400 kbit/s guaranteed transfer rate. It uses 8-bit subaddressing with an
auto-increment function. All registers are write and read, except two read only status
bytes.
The register bit map consists of an RGB Look-Up Table (LUT), a cursor bit map and
control registers. The LUT contains three banks of 256 bytes, where each RGB triplet is
assigned to one address. Thus a write access needs the LUT address and three data
bytes following subaddress FFh. For further write access auto-incrementing of the LUT
address is performed. The cursor bit map access is similar to the LUT access but contains
only a single byte per address.
The I
In order to reduce the power consumption, the SAA7104E; SAA7105E supports
2 Power-down modes, accessible via the I
(DOWNA = 1) turns off the digital-to-analog converters and the pixel clock synthesizer.
The digital Power-down mode (DOWND = 1) turns off all internal clocks and sets the
digital outputs to LOW except the I
can still be accessed in this mode, however not all registers can be read or written to.
Reading or writing to the look-up tables, the cursor and the HD sync generator require a
valid pixel clock. The typical supply current in full power-down is approximately 5 mA.
Because the analog Power-down mode turns off the pixel clock synthesizer, there are
limitations in some applications. If there is no pixel clock, the IC is not able to set its
outputs to LOW. So, in most cases, DOWNA and DOWND should be set to logic 1
simultaneously. If the EIDIV bit is logic 1, it should be set to logic 0 before power-down.
The SAA7104E; SAA7105E needs to provide a continuous data stream at its analog
outputs as well as receive a continuous stream of data from its data source. Because
there is no frame memory isolating the data streams, restrictions apply to the input frame
timings.
Input and output processing of the SAA7104E; SAA7105E are only coupled through the
vertical frequencies. In Master mode, the encoder provides a vertical sync and an
odd/even pulse to the input processing. In Slave mode, the encoder receives them.
The parameters of the input field are mainly given by the memory capacity of the
SAA7104E; SAA7105E. The rule is that the scaler and thus the input processing needs to
provide the video data in the same time frames as the encoder reads them. Therefore, the
vertical active video times (and the vertical frequencies) need to be the same.
The second rule is that there has to be data in the buffer FIFO when the encoder enters
the active video area. Therefore, the vertical offset in the input path needs to be a bit
shorter than the offset of the encoder.
2
C-bus interface
2
2
C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses
C-bus slave address is defined as 88h.
Rev. 02 — 23 December 2005
2
C-bus interface. The IC keeps its programming and
SAA7104E; SAA7105E
2
C-bus. The analog Power-down mode
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Digital video encoder
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