SAA7105E/V1/G NXP Semiconductors, SAA7105E/V1/G Datasheet - Page 10

• Manufacturer Part Number: SAA7105E/V1/G
• Description: Video ICs PC-DENC
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant
• Other names: SAA7105E/V1/G,557

Philips Semiconductors
SAA7104E_SAA7105E_2
Product data sheet
7.2 Input formatter
7.3 RGB LUT
7.4 Cursor insertion
The input formatter converts all accepted PD input data formats, either RGB or Y-C
to a common internal RGB or Y-C
When double-edge clocking is used, the data is internally split into portions PPD1 and
PPD2. The clock edge assignment must be set according to the I
and EDGE for correct operation.
If Y-C
be used directly to feed the video encoder block.
The horizontal upscaling is supported via the input formatter. According to the
programming of the pixel clock dividers (see
stream to 1 , 2 or 4 the input data rate. An optional interpolation filter is available. The
clock domain transition is handled by a 4 entries wide FIFO which gets initialized every
field or explicitly at request. A bypass for the FIFO is available, especially for high input
data rates.
The three 256 byte RAMs of this block can be addressed by three 8-bit wide signals, thus
it can be used to build any transformation, e.g. a gamma correction for RGB signals. In the
event that the indexed color data is applied, the RAMs are addressed in parallel.
The LUTs can either be loaded by an I
input through the PD port. In the latter case, 256 bytes
are expected at the beginning of the input video line, two lines before the line that has
been defined as first active line, until the middle of the line immediately preceding the first
active line. The first 3 bytes represent the first RGB LUT data, and so on.
A 32 dots
uploaded by an I
the PD port. In the latter case, the 256 bytes defining the cursor bit map (2 bits per pixel)
are expected immediately following the last RGB LUT data in the line preceding the first
active line.
The cursor bit map is set up as follows: each pixel occupies 2 bits. The meaning of these
bits depends on the CMODE I
that the input pixels are passed through, the ‘cursor colors’ can be programmed in
separate registers.
The bit map is stored with 4 pixels per byte, aligned to the least significant bit. So the first
pixel is in bits 0 and 1, the next pixel in bits 3 and 4 and so on. The first index is the
column, followed by the row; index 0,0 is the upper left corner.
Table 6:
D1
7
B
pixel n + 3
-C
R
is being applied as a 27 MB/s data stream, the output of the input formatter can
Layout of a byte in the cursor bit map
32 dots cursor can be overlaid as an option; the bit map of the cursor can be
D0
6
2
C-bus write access to specific registers or in the pixel data input through
Rev. 02 — 23 December 2005
D1
5
pixel n + 2
2
C-bus register as described in
B
-C
R
D0
2
4
data stream.
C-bus write access or can be part of the pixel data
SAA7104E; SAA7105E
Section
D1
3
pixel n + 1
7.10), it will sample up the data
3 bytes for the R, G and B LUT
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
D0
2
Table
2
C-bus control bits SLOT
Digital video encoder
8. Transparent means
D1
1
pixel n
D0
10 of 78
B
0
-C
R
,