SAA7105E/V1/G NXP Semiconductors, SAA7105E/V1/G Datasheet - Page 49

• Manufacturer Part Number: SAA7105E/V1/G
• Description: Video ICs PC-DENC
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant
• Other names: SAA7105E/V1/G,557

Philips Semiconductors
SAA7104E_SAA7105E_2
Product data sheet
Table 68:
Table 69:
Bit
7
6
5
4
3
2
1 and 0 YPIX[9:8]
Bit
7
6
5
4
3
Symbol
EFS
PCBN
SLAVE
ILC
YFIL
-
Symbol
HFS
VFS
OFS
PFS
OVS
Scaler CTRL, MCB and YPIX register, subaddress 96h, bit description
Sync control register, subaddress 97h, bit description
Access Value Description
R/W
R/W
R/W
R/W
R/W
R/W
Access Value Description
R/W
R/W
R/W
R/W
R/W
Rev. 02 — 23 December 2005
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
in Slave mode frame sync signal at pin FSVGC
ignored
accepted
polarity of CBO signal
normal (HIGH during active video)
inverted (LOW during active video)
from the SAA7104E; SAA7105E the timing to the graphics
controller is
master
slave
if hardware cursor insertion is active
set LOW for non-interlaced input signals
set HIGH for interlaced input signals
luminance sharpness booster
disabled
enabled
must be programmed with logic 0 to ensure compatibility to
future enhancements
see
horizontal sync is derived from
input signal (Save mode) at pin HSVGC
a frame sync signal (Slave mode) at pin FSVGC (only if EFS
is set HIGH)
vertical sync (field sync) is derived from
input signal (Slave mode) at pin VSVGC
a frame sync signal (Slave mode) at pin FSVGC (only if EFS
is set HIGH)
pin FSVGC is
input
active output
polarity of signal at pin FSVGC in output mode (Master
mode) is
active HIGH; rising edge of the input signal is used in Slave
mode
active LOW; falling edge of the input signal is used in Slave
mode
pin VSVGC is
input
active output
Table 67
SAA7104E; SAA7105E
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Digital video encoder
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