SAA7105E/V1/G NXP Semiconductors, SAA7105E/V1/G Datasheet - Page 21

• Manufacturer Part Number: SAA7105E/V1/G
• Description: Video ICs PC-DENC
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant
• Other names: SAA7105E/V1/G,557

Philips Semiconductors
SAA7104E_SAA7105E_2
Product data sheet
7.20.1 TV display window
7.20.2 Input frame and pixel clock
The following Sections give the set of equations required to program the IC for the most
common application: A post processor in Master mode with non-interlaced video input
data.
Some variables are defined below:
At 60 Hz, the first visible pixel has the index 256, 710 pixels can be encoded; at 50 Hz, the
index is 284, 702 pixels can be visible.
The output lines should be centred on the screen. It should be noted that the encoder has
2 clocks per pixel; see
ADWHS = 256 + 710
ADWHE = ADWHS + OutPix
For vertical, the procedure is the same. At 60 Hz, the first line with video information is
number 19, 240 lines can be active. For 50 Hz, the numbers are 23 and 287; see
to
LAL = FAL + OutLin (all frequencies)
Most TV sets use overscan, and not all pixels respectively lines are visible. There is no
standard for the factor, it is highly recommended to make the number of output pixels and
lines adjustable. A reasonable underscan factor is 10 %, giving approximately 640 output
pixels per line.
The total number of pixel clocks per line and the input horizontal offset need to be chosen
next. The only constraint is that the horizontal blanking has at least 10 clock pulses.
The required pixel clock frequency can be determined in the following way: Due to the
limited internal FIFO size, the input path has to provide all pixels in the same time frame
as the encoders vertical active time. The scaler also has to process the first and last
border lines for the anti-flicker function. Thus:
FAL
TPclk
•
•
•
•
•
•
•
•
Table
InPix: the number of active pixels per input line
InPpl: the length of the entire input line in pixel clocks
InLin: the number of active lines per input field/frame
TPclk: the pixel clock period
RiePclk: the ratio of internal to external pixel clock
OutPix: the number of active pixels per output line
OutLin: the number of active lines per output field
TXclk: the encoder clock period (37.037 ns)
=
=
19
57.
----------------------------------------------------------------------------------- -
InPpl integer
+
240 OutLin
------------------------------- -
262.5 1716 TXclk
–
2
Rev. 02 — 23 December 2005
Table
OutPix (60 Hz); ADWHS = 284 + 702
InLin
--------------------- -
OutLin
(60 Hz);
47.
+
2 (all frequencies)
2
FAL
262.5
=
SAA7104E; SAA7105E
(60 Hz)
23
+
287 OutLin
------------------------------- -
–
2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
(50 Hz);
OutPix (50 Hz);
Digital video encoder
Table 55
21 of 78