SAA7105E/V1/G NXP Semiconductors, SAA7105E/V1/G Datasheet - Page 12

• Manufacturer Part Number: SAA7105E/V1/G
• Description: Video ICs PC-DENC
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant
• Other names: SAA7105E/V1/G,557

Philips Semiconductors
SAA7104E_SAA7105E_2
Product data sheet
7.7 Vertical scaler and anti-flicker filter
7.8 FIFO
7.9 Border generator
If the SAA7104E; SAA7105E input data is in accordance with ‘ITU-R BT.656’ , the scaler
enters another mode. In this event, XINC needs to be set to 2048 for a scaling factor of 1.
With higher values, upscaling will occur.
The phase resolution of the circuit is 12 bits, giving a maximum offset of 0.2 after
800 input pixels. Small FIFOs rearrange a 4 : 2 : 2 data stream at the scaler output.
The functions scaling, Anti-Flicker Filter (AFF) and re-interlacing are implemented in the
vertical scaler.
Besides the entire input frame, it receives the first and last lines of the border to allow
anti-flicker filtering.
The circuit generates the interlaced output fields by scaling down the input frames with
different offsets for odd and even fields. Increasing the YSKIP setting reduces the
anti-flicker function. A YSKIP value of 4095 switches it off; see
An additional, programmable vertical filter supports the anti-flicker function. This filter is
not available at upscaling factors of more than 2.
The programming is similar to the horizontal scaler. For the re-interlacing, the resolutions
of the offset registers are not sufficient, so the weighting factors for the first lines can also
be adjusted. YINC = 0 sets the scaling factor to 1; YIWGTO and YIWGTE must not be 0.
Due to the re-interlacing, the circuit can perform upscaling by a maximum factor of 2. The
maximum factor depends on the setting of the anti-flicker function and can be derived from
the formulae given in
An additional upscaling mode allows to increase the upscaling factor to maximum 4 as it is
required for the old VGA modes like 320
The FIFO acts as a buffer to translate from the PIXCLK clock domain to the XTAL clock
domain. The write clock is PIXCLK and the read clock is XTAL. An underflow or overflow
condition can be detected via the I
In order to avoid underflows and overflows, it is essential that the frequency of the
synthesized PIXCLK matches to the input graphics resolution and the desired scaling
factor.
When the graphics picture is to be displayed as interlaced PAL, NTSC, S-video or RGB on
a TV screen, it is desired in many cases not to lose picture information due to the inherent
overscanning of a TV set. The desired amount of underscan area, which is achieved
through appropriate scaling in the vertical and horizontal direction, can be filled in the
border generator with an arbitrary true color tint.
Rev. 02 — 23 December 2005
Section
7.20.
2
C-bus read access.
SAA7104E; SAA7105E
240.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Table
Digital video encoder
78.
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