SAA7105E/V1/G NXP Semiconductors, SAA7105E/V1/G Datasheet - Page 43

• Manufacturer Part Number: SAA7105E/V1/G
• Description: Video ICs PC-DENC
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant
• Other names: SAA7105E/V1/G,557

Philips Semiconductors
SAA7104E_SAA7105E_2
Product data sheet
Table 44:
Legend: * = default value after reset.
[1]
[2]
Table 45:
Legend: * = default value after reset.
Subaddress Bit
6Ch
6Dh
Bit
7
6
5 and 4 PHRES[1:0] R/W
3 and 2 LDEL[1:0]
1 and 0 FLC[1:0]
Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases delays of
all internally generated timing signals.
Increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG = 0 to 31 (1Fh).
Symbol
NVTRIG
BLCKON
Trigger control registers, subaddresses 6Ch and 6Dh, bit description
Multi control register, subaddress 6Eh, bit description
7 to 0 HTRIG[7:0]
7 to 5 HTRIG[10:8] R/W
4 to 0 VTRIG[4:0]
Symbol
Rev. 02 — 23 December 2005
Access Value Description
R/W
R/W
R/W
R/W
0
1
0*
1
00
01
10
11
00*
01
10
11
00*
01
10
11
Access Value Description
R/W
R/W
values of the VTRIG register are
positive
negative
encoder in normal operation mode
output signal is forced to blanking level
selects the phase reset mode of the color subcarrier
generator
no subcarrier reset
subcarrier reset every two lines
subcarrier reset every eight fields
subcarrier reset every four fields
selects the delay on luminance path with reference to
chrominance path
no luminance delay
1 LLC luminance delay
2 LLC luminance delay
3 LLC luminance delay
field length control
interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at
60 Hz
non-interlaced 312 lines/field at 50 Hz, 262 lines/field at
60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at
60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at
60 Hz
SAA7104E; SAA7105E
00h*
0h*
00h*
sets the horizontal trigger phase related to
chip-internal horizontal input
sets the vertical trigger phase related to
chip-internal vertical input
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Digital video encoder
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