SAA7105E/V1/G NXP Semiconductors, SAA7105E/V1/G Datasheet - Page 23

• Manufacturer Part Number: SAA7105E/V1/G
• Description: Video ICs PC-DENC
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant
• Other names: SAA7105E/V1/G,557

Philips Semiconductors
SAA7104E_SAA7105E_2
Product data sheet
7.21 Input levels and formats
When YINC = 0 it sets the scaler to scaling factor 1. The initial weighting factors must not
be set to 0 in this case. YIWGTE may go negative. In this event, YINC should be added
and YOFSE incremented. This can be repeated as often as necessary to make YIWGTE
positive.
It should be noted that these equations assume that the input is non-interlaced but the
output is interlaced. If the input is interlaced, the initial weighting factors need to be
adapted to obtain the proper phase offsets in the output frame.
If vertical upscaling beyond the upper capabilities is required, the parameter YUPSC may
be set to logic 1. This extends the maximum vertical scaling factor by a factor of 2. Only
the parameter YINC is affected, it needs to be divided by two to get the same effect.
There are restrictions in this mode:
The SAA7104E; SAA7105E accepts digital Y, C
codes) in accordance with ‘ITU-R BT.601’ . An optional gain adjustment also allows to
accept data with the full level swing of 0 to 255.
For C and CVBS outputs, deviating amplitudes of the color difference signals can be
compensated for by independent gain control setting, while gain for luminance is set to
predefined values, distinguishable for 7.5 IRE set-up or without set-up.
The RGB, respectively C
(GY) and color difference signals (GCD). Reference levels are measured with a color bar,
100 % white, 100 % amplitude and 100 % saturation.
The SAA7104E; SAA7105E has special input cells for the VGC port. They operate at a
wider supply voltage range and have a strict input threshold at
speed of these cells, the EIDIV bit needs to be set to logic 1. Note that the impedance of
these cells is approximately 6 k . This may cause trouble with the bootstrapping pins of
some graphic chips. So the power-on reset forces the bit to logic 0, the input impedance is
regular in this mode.
YIWGTO
YIWGTE
•
•
The vertical filter YFILT is not available in this mode; the circuit will ignore this value
The horizontal blanking needs to be long enough to transfer an output line between
2 memory locations. This is 710 internal pixel clocks.
Or the upscaling factor needs to be limited to 1.5 and the horizontal upscaling factor is
also limited to less than 1.5. In this case a normal blanking length is sufficient.
=
=
YINC YSKIP
------------------------------------- -
YINC
------------- -
2
–
+
2
2048
Rev. 02 — 23 December 2005
R
-Y-C
B
path features an individual gain setting for luminance
SAA7104E; SAA7105E
B
, C
R
or RGB data with levels (digital
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
1
2
V
Digital video encoder
DDD
. To achieve full
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