SAA7105E/V1/G NXP Semiconductors, SAA7105E/V1/G Datasheet - Page 53

• Manufacturer Part Number: SAA7105E/V1/G
• Description: Video ICs PC-DENC
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant
• Other names: SAA7105E/V1/G,557

Philips Semiconductors
SAA7104E_SAA7105E_2
Product data sheet
Table 87:
Table 88:
Table 89:
Table 90:
Table 91:
Data byte
HLPA
HPD
HPV
Byte
0
1
2
3
4
5
6
7
Data byte
HPVA
HPVE
HHS
HVS
Byte
0
1
Bit
7 to 0 HLCT[7:0] with HLCT[9:8] (see
Symbol
Subaddress D2h
Layout of the data bytes in the line pattern array
Subaddress D3h
Layout of the data bytes in the value array
HD sync trigger state 1 register, subaddress D4h, bit description
Description
RAM start address for the HD sync line pattern array; the byte following
subaddress D2 points to the first cell to be loaded with the next transmitted byte;
succeeding cells are loaded by auto-incrementing until stop condition. Each line
pattern array entry consists of 4 value-duration pairs occupying 2 bytes;
see
HD pattern duration. The value defines the time in pixel clocks (HPD + 1) the
corresponding value HPV is added to the HD output signal. If 0, this entry will be
skipped.
HD pattern value pointer. This gives the index in the HD value array containing the
level to be inserted into the HD output path. If the MSB of HPV is logic 1, the value
will only be inserted into the Y/GREEN channel of the HD data path, the other
channels remain unchanged.
Description
HPD07
HPV03
HPD17
HPV13
HPD27
HPV23
HPD37
HPV33
Description
RAM start address for the HD sync value array; the byte following subaddress D3
points to the first cell to be loaded with the next transmitted byte; succeeding cells
are loaded by auto-incrementing until stop condition. Each line pattern array entry
consists of 2 bytes. The array has 8 entries.
HD pattern value entry. The HD path will insert a level of (HPV + 52)
the data path. The value is signed 8-bits wide; see
HD horizontal sync. If the HD engine is active, this value will be provided at
pin HSM_CSYNC; see
HD vertical sync. If the HD engine is active, this value will be provided at pin VSM;
see
Description
HPVE7
0
Table
Table
Description
backwards)
Rev. 02 — 23 December 2005
88. The array has 7 entries.
90.
HPD06
HPV02
HPD16
HPV12
HPD26
HPV22
HPD36
HPV32
HPVE6
0
HPD05
HPV01
HPD14
HPV11
HPD25
HPV21
HPD35
HPV31
HPVE5
0
Table
Table
90.
SAA7104E; SAA7105E
0
HPD04
HPV00
HPD14
HPV10
HPD24
HPV20
HPD34
HPV30
HPVE4
92) state of the HD line counter after trigger (counts
0
HPD03
0
HPD13
0
HPD23
0
HPD33
0
HPVE3
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Table
0
HPD02
0
HPD12
0
HPD22
0
HPD32
0
HPVE2
90.
Digital video encoder
HVS
HPD01
HPD09
HPD11
HPD19
HPD21
HPD29
HPD31
HPD39
HPVE1
0.66 IRE into
HHS
HPD00
HPD08
HPD10
HPD18
HPD20
HPD28
HPD30
HPD38
HPVE0
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