SAA7105E/V1/G NXP Semiconductors, SAA7105E/V1/G Datasheet - Page 15

• Manufacturer Part Number: SAA7105E/V1/G
• Description: Video ICs PC-DENC
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant
• Other names: SAA7105E/V1/G,557

Philips Semiconductors
SAA7104E_SAA7105E_2
Product data sheet
7.13 RGB processor
7.14 Triple DAC
7.15 HD data path
7.16 Timing generator
This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be
fed to a SCART plug.
Before Y, C
difference signals and 2 times oversampling for luminance and 4 times oversampling for
color difference signals is performed. The transfer curves of luminance and color
difference components of RGB are illustrated in
Both Y and C signals are converted from digital-to-analog in a 10-bit resolution at the
output of the video encoder. Y and C signals are also combined into a 10-bit CVBS signal.
The CVBS output signal occurs with the same processing delay as the Y, C and optional
RGB or C
by
RED, GREEN and BLUE signals are also converted from digital-to-analog, each providing
a 10-bit resolution.
The reference currents of all three DACs can be adjusted individually in order to adapt for
different output signals. In addition, all reference currents can be adjusted commonly to
compensate for small tolerances of the on-chip band gap reference voltage.
Alternatively, all currents can be switched off to reduce power dissipation.
All three outputs can be used to sense for an external load (usually 75 ) during a
pre-defined output. A flag in the I
not. In addition, an automatic sense mode can be activated which indicates a 75
any of the three outputs at the dedicated interrupt pin TVD.
If the SAA7104E; SAA7105E is required to drive a second (auxiliary) VGA monitor or an
HDTV set, the DACs receive the signal coming from the HD data path. In this event, the
DACs are clocked at the incoming PIXCLKI instead of the 27 MHz crystal clock used in
the video encoder.
This data path allows the SAA7104E; SAA7105E to be used with VGA or HDTV monitors.
It receives its data directly from the cursor generator and supports RGB and Y-P
output formats (RGB not with Y-P
A gain adjustment either leads the full level swing to the digital-to-analog converters or
reduces the amplitude by a factor of 0.69. This enables sync pulses to be added to the
signal as it is required for display units expecting signals with sync pulses, either regular or
3-level syncs.
The synchronization of the SAA7104E; SAA7105E is able to operate in two modes; Slave
mode and Master mode.
15
16
with respect to Y and C DACs to make maximum use of the conversion ranges.
R
-Y-C
B
and C
B
outputs. Absolute amplitude at the input of the DAC for CVBS is reduced
R
signals are de-matrixed, individual gain adjustment for Y and color
Rev. 02 — 23 December 2005
2
B
C-bus status byte reflects whether a load is applied or
-P
R
input formats). No scaling is done in this mode.
SAA7104E; SAA7105E
Figure 10
and
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Figure
Digital video encoder
11.
B
-P
load at
15 of 78
R