SAA7105E/V1/G NXP Semiconductors, SAA7105E/V1/G Datasheet - Page 16

• Manufacturer Part Number: SAA7105E/V1/G
• Description: Video ICs PC-DENC
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant
• Other names: SAA7105E/V1/G,557

Philips Semiconductors
SAA7104E_SAA7105E_2
Product data sheet
7.17 Pattern generator for HD sync pulses
In Slave mode, the circuit accepts sync pulses on the bidirectional FSVGC (frame sync),
VSVGC (vertical sync) and HSVGC (horizontal sync) pins: the polarities of the signals can
be programmed. The frame sync signal is only necessary when the input signal is
interlaced, in other cases it may be omitted. If the frame sync signal is present, it is
possible to derive the vertical and the horizontal phase from it by setting the HFS and VFS
bits. HSVGC and VSVGC are not necessary in this case, so it is possible to switch the
pins to output mode.
Alternatively, the device can be triggered by auxiliary codes in a ITU-R BT.656 data
stream via PD7 to PD0.
Only vertical frequencies of 50 Hz and 60 Hz are allowed with the SAA7104E;
SAA7105E. In Slave mode, it is not possible to lock the encoders color carrier to the line
frequency with the PHRES bits.
In the (more common) Master mode, the time base of the circuit is continuously
free-running. The IC can output a frame sync at pin FSVGC, a vertical sync at pin VSVGC,
a horizontal sync at pin HSVGC and a composite blanking signal at pin CBO. All of these
signals are defined in the PIXCLK domain. The duration of HSVGC and VSVGC are fixed,
they are 64 clocks for HSVGC and 1 line for VSVGC. The leading slopes are in phase and
the polarities can be programmed.
The input line length can be programmed. The field length is always derived from the field
length of the encoder and the pixel clock frequency that is being used.
CBO acts as a data request signal. The circuit accepts input data at a programmable
number of clocks after CBO goes active. This signal is programmable and it is possible to
adjust the following (see
In most cases, the vertical offsets for odd and even fields are equal. If they are not, then
the even field will start later. The SAA7104E; SAA7105E will also request the first input
lines in the even field, the total number of requested lines will increase by the difference of
the offsets.
As stated above, the circuit can be programmed to accept the look-up and cursor data in
the first 2 lines of each field. The timing generator provides normal data request pulses for
these lines; the duration is the same as for regular lines. The additional request pulses will
be suppressed with LUTL set to logic 0; see
change in this case, so the first active line can be number 2, counted from 0.
The pattern generator provides appropriate synchronization patterns for the video data
path in auxiliary monitor or HDTV mode. It provides maximum flexibility in terms of raster
generation for all interlaced and non-interlaced computer graphics or ATSC formats. The
sync engine is capable of providing a combination of event-value pairs which can be used
•
•
•
•
•
The horizontal offset
The length of the active part of the line
The distance from active start to first expected data
The vertical offset separately for odd and even fields
The number of lines per input field
Rev. 02 — 23 December 2005
Figure 13
and
Figure
SAA7104E; SAA7105E
Table
14):
103. The other vertical timings do not
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Digital video encoder
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