saa7105e NXP Semiconductors, saa7105e Datasheet
saa7105e
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... DATA SHEET SAA7104E; SAA7105E Digital video encoder Product specification INTEGRATED CIRCUITS 2004 Mar 04 ...
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... RGB processor 7.14 Triple DAC 7.15 HD data path 7.16 Timing generator 7.17 Pattern generator for HD sync pulses 2 7.18 I C-bus interface 7.19 Power-down modes 7.20 Programming the SAA7104E; SAA7105E 7.21 Input levels and formats 7.22 Bit allocation map 2 7.23 I C-bus format 7.24 Slave receiver 7.25 Slave transmitter 8 BOUNDARY SCAN TEST 8.1 Initialization of boundary scan circuit 8 ...
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... RGB Look-Up Table (LUT) Support for hardware cursor HDTV up to 1920 1080 interlaced and 1280 progressive, including 3-level sync pulses 2004 Mar 04 SAA7104E; SAA7105E Programmable border colour of underscan area Programmable 5 line anti-flicker filter On-chip 27 MHz crystal oscillator (3rd-harmonic or fundamental 27 MHz crystal) 2 ...
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... Philips Semiconductors Digital video encoder 2 GENERAL DESCRIPTION The SAA7104E; SAA7105E is an advanced next-generation video encoder which converts PC graphics data at maximum 1280 (optionally 1920 1080 interlaced) to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and anti-flicker filter (maximum 5 lines) ensures properly sized and flicker-free TV display as CVBS or S-video output ...
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... A10, B9 C9, D9 C1, C2, B1, B2, A2, B4, B3, A3, F3, H1, H2, H3 PD11 to INPUT PD0 FORMATTER UPSAMPLING DECIMATOR HORIZONTAL PIXCLKI FIFO GENERATOR SAA7104E SAA7105E G4 PIXEL CLOCK PIXCLKO SYNTHESIZER OSCILLATOR SSA1 SSA2 DDD1 DDD2 DDD3 DDD4 SSD1 ...
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... Boundary Scan Test (BST); note 2 S digital supply voltage 2 (3.3 V for I/Os) S digital supply voltage 3 (3.3 V for core) S digital supply voltage 4 (3.3 V for core) S analog supply voltage 3 (3.3 V for oscillator) 6 Product specification SAA7104E; SAA7105E DESCRIPTION resistor to analog ground or CVBS signal CVBS signal R ...
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... VGC I MSB 5 with C -Y see Tables for B R pin assignment I MSB 6 with C -Y see Tables for B R pin assignment I MSB 7 with C -Y see Tables for B R pin assignment 7 Product specification SAA7104E; SAA7105E DESCRIPTION ...
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... TDI V DUMP V V DDA2 SSA1 V DDA4 V BLUE_ GREEN_ RED_ V SSD1 V CB_ VBS_ CR_ SSD2 V CVBS CVBS C_ SSD3 V CVBS SSD4 V V VSM HSM_ V SSD1 DDA3 V CSYNC SSD2 V SSD3 V SSD4 8 Product specification SAA7104E; SAA7105E DDA1 DDA1 DDA1 DDA1 reserved TVD 14 ...
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... PC-DVD; for that the anti-flicker filter, and in most cases the scaler, will simply be bypassed. Besides the applications for video output, the SAA7104E; SAA7105E can also be used for generating a kind of auxiliary VGA output, when the RGB non-interlaced input signal is fed to the DACs. This may be of interest for example, when the graphics controller provides a second graphics window at its video output port ...
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... HSM_CSYNC) can be generated; it can be advanced periods of the 27 MHz crystal clock in order to be adapted to the RGB processing set. The SAA7104E; SAA7105E synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals from that clock. Wide screen signalling data can be loaded via the I and is inserted into line 23 for standards using field rate ...
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... C-bus write ... 6 7 ... 254 255 Table 5 Cursor modes CURSOR PATTERN pixel Product specification SAA7104E; SAA7105E row 0 row 0 row 0 column 3 column 2 column 1 row 0 row 0 row 0 column 7 column 6 column 5 row 0 row 0 row 0 column column ...
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... Each input pixel is a programmable fraction of the current output pixel (XINC/4096). A special case is XINC = 0, this sets the scaling factor the SAA7104E; SAA7105E input data is in accordance with “ITU-R BT.656” , the scaler enters another mode. In this event, XINC needs to be set to 2048 for a scaling factor of 1 ...
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... The actual line number in which data encoded, can be modified in a certain range. The data clock frequency is in accordance with the definition for NTSC M standard 32 times horizontal line frequency. 13 Product specification SAA7104E; SAA7105E ( ELETEXT INSERTION AND ENCODING - TIME CONTROL P S (VPS) ...
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... TVD. 2004 Mar 04 If the SAA7104E; SAA7105E is required to drive a second (auxiliary) VGA monitor or an HDTV set, the DACs receive the signal coming from the HD data path. In this event, the DACs are clocked at the incoming PIXCLKI instead of the 27 MHz crystal clock used in the video encoder ...
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... In most cases, the vertical offsets for odd and even fields are equal. If they are not, then the even field will start later. The SAA7104E; SAA7105E will also request the first input lines in the even field, the total number of requested lines will increase by the difference of the offsets. ...
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Acrobat reader. white to force landscape pages to be ... handbook, full pagewidth 4-bit line type index line type pointer 8 2-bit value VALUE ...
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... Reading of the arrays is possible but all address pointers must be initialized before the next write operation. COMMENT value( value(3); (subtract 1 from real duration) value( value(3) value(0) + 960 value( value( value(3) value(3) + 960 value( Product specification SAA7104E; SAA7105E value(3) value(3) sync-black-null-black) ...
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... EIDIV bit is logic 1, it should be set to logic 0 before power-down. 7.20 Programming the SAA7104E; SAA7105E The SAA7104E; SAA7105E needs to provide a continuous data stream at its analog outputs as well as receive a continuous stream of data from its data source. Because there is no frame memory isolating the data streams, restrictions apply to the input frame timings. Input and output processing of the SAA7104E ...
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... The only constraint is that the horizontal blanking has at least 10 clock pulses. 2004 Mar 04 SAA7104E; SAA7105E The required pixel clock frequency can be determined in the following way: Due to the limited internal FIFO size, the input path has to provide all pixels in the same time frame as the encoders vertical active time ...
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... The SAA7104E; SAA7105E has special input cells for the VGC port. They operate at a wider supply voltage range and have a strict input threshold at speed of these cells, the EIDIV bit needs to be set to logic 1 ...
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... R R0/C 0 PD0 R G7/Y7 Table 12 Pin assignment for input format 3 G6/ 8-BIT NON-INTERLACED C G5/Y5 G4/Y4 PIN PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 21 Product specification SAA7104E; SAA7105E FALLING RISING CLOCK EDGE CLOCK EDGE FALLING RISING ...
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... PD6 C 3(0) Y3(1) R PD5 C 2(0) Y2(1) R PD4 C 1(0) Y1(1) R PD3 C 0(0) Y0(1) R PD2 PD1 PD0 RISING CLOCK EDGE Product specification SAA7104E; SAA7105E RGB/C -Y FALLING RISING CLOCK EDGE CLOCK EDGE G4/Y4 R7 G3/Y3 R6 G2/Y2 R5 B7 B6 B5/C 5 G7/Y7 B B4/C 4 ...
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Acrobat reader. white to force landscape pages to be ... 7.22 Bit allocation map Table 16 Slave receiver (slave address 88H) SUB REGISTER FUNCTION ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. (HEX) Gain U 5B Gain V 5C Gain U MSB, ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. (HEX) TTX even request vertical end 79 First active line ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. (HEX) Blank enable for NI-bypass, A1 vertical line skip MSB ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. (HEX) Input path control FD Cursor bit map FE Colour ...
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... If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed. 2004 Mar 04 SUBADDRESS A DATA 0 RAM ADDRESS A DATA 00 A RAM ADDRESS A RAM ADDRESS A DATA DESCRIPTION 28 Product specification SAA7104E; SAA7105E A -------- DATA n A DATA 01 A -------- DATA n DATA 0 A -------- DATA n A DATA 0G A DATA ...
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... BLUE DAC; default after reset is 1FH for output of CVBS signal 00000b 0.585 V to 11111b Table 27 Subaddress 1AH DATA BYTE MSMT monitor sense mode threshold for DAC output voltage, should be set to 70 2004 Mar 04 SAA7104E; SAA7105E DESCRIPTION GAIN (%) ...
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... DATA BYTE LEVEL BS starting point of burst in clock cycles 2004 Mar 04 DESCRIPTION DESCRIPTION DESCRIPTION PAL (21H); default after reset if strapping pin FSVGC tied to HIGH NTSC (19H); default after reset if strapping pin FSVGC tied to LOW 30 Product specification SAA7104E; SAA7105E REMARKS ...
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... HIGH impulse resets synchronization of the encoder (first field, first line) PAL (1DH); default after reset if strapping pin FSVGC tied to HIGH NTSC (1DH); default after reset if strapping pin FSVGC tied to LOW DESCRIPTION DESCRIPTION 31 Product specification SAA7104E; SAA7105E REMARKS ) signal B ) signal R ...
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... Suggested nominal value = 0, depending on external application. GCD4 to GCD0 Gain colour difference of RGB (C (1 application. 2004 Mar 04 DESCRIPTION DESCRIPTION DESCRIPTION , Y and C ) output, ranging from ( and Suggested nominal value = 0, depending on external Product specification SAA7104E; SAA7105E output, ranging from ...
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... VPS14 fourteenth byte of video programming system data 2004 Mar 04 DESCRIPTION to RGB dematrix is active; default after reset to RGB dematrix is bypassed DESCRIPTION DESCRIPTION 33 Product specification SAA7104E; SAA7105E REMARKS in line 16; LSB first; all other bytes are not relevant for VPS ...
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... BLCKL = 63 (3FH); note 1 output black level = 49 IRE white-to-sync = 143 IRE; recommended value: BLCKL = 51 (33H) note 2 BLCKL = 0; note 2 output black level = 27 IRE BLCKL = 63 (3FH); note 2 output black level = 47 IRE 2/6.29 + 28.9. 2/6.18 + 26.5. 34 Product specification SAA7104E; SAA7105E RESULT REMARKS nominal to +2.16 nominal nominal to +2.04 nominal REMARKS nominal to +1.55 nominal nominal to +1.46 ...
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... BLNNL = 63 (3FH); note 1 output blanking level = 45 IRE white-to-sync = 143 IRE; recommended value: BLNNL = 53 (35H) note 2 BLNNL = 0; note 2 output blanking level = 26 IRE BLNNL = 63 (3FH); note 2 output blanking level = 46 IRE 2/6.29 + 25.4. 2/6.18 + 25.9; default after reset: 35H. DESCRIPTION DESCRIPTION 35 Product specification SAA7104E; SAA7105E REMARKS ...
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... IRE; PAL encoding BSTA = 0 to 2.82 white-to-black = 100 IRE; burst = 43 IRE; NTSC encoding BSTA = 0 to 1.90 white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 3.02 36 Product specification SAA7104E; SAA7105E 2 C-bus address CONDITIONS REMARKS recommended value: BSTA = 63 (3FH) nominal recommended value: BSTA = 45 (2DH) ...
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... LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the definition of line 21 encoding format. DESCRIPTION DESCRIPTION DESCRIPTION 37 Product specification SAA7104E; SAA7105E REMARKS FSC3 = most significant byte fsc ------- - 2 ; ...
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... Table 58 Logic levels and function of CCEN DATA BYTE CCEN1 CCEN0 0 0 line 21 encoding off; default after reset 0 1 enables encoding in field 1 (odd enables encoding in field 2 (even enables encoding in both fields 2004 Mar 04 SAA7104E; SAA7105E DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 38 Product specification ...
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... TTXOVE for other systems 2004 Mar 04 DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 39 Product specification SAA7104E; SAA7105E REMARKS TTXHS = 42H; is default after reset if strapped to PAL TTXHS = 54H; is default after reset if strapped to NTSC REMARKS minimum value: TTXHD = 2; is default after reset REMARKS TTXOVS = 05H ...
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... DESCRIPTION DESCRIPTION MHz nominal, e.g. 640 XTAL XTAL 40 Product specification SAA7104E; SAA7105E REMARKS TTXEVS = 04H; is default after reset if strapped to PAL TTXEVS = 05H; is default after reset if strapped to NTSC TTXEVE = 16H; is default after reset if strapped to PAL TTXEVE = 10H; is default after reset if strapped to NTSC 480 to NTSC M: PCL = 20F63BH ...
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... FIFO internal transfers; nominal value is 8; default after reset Table 73 Subaddresses 90H and 94H DATA BYTE XOFS horizontal offset; defines the number of PIXCLKs from horizontal sync (HSVGC) output to composite blanking (CBO) output 2004 Mar 04 SAA7104E; SAA7105E DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 41 ...
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... CBO signal (HIGH during active video) 1 inverted polarity of CBO signal (LOW during active video) SLAVE 0 the SAA7104E; SAA7105E is timing master to the graphics controller 1 the SAA7104E; SAA7105E is timing slave to the graphics controller ILC 0 if hardware cursor insertion is active, set LOW for non-interlaced input signals ...
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... HLEN horizontal length; Table 81 Subaddress 99H DATA BYTE IDEL input delay; defines the distance in PIXCLKs between the active edge of CBO and the first received valid pixel 2004 Mar 04 DESCRIPTION DESCRIPTION number of PIXCLKs HLEN ---------------------------------------------------- - 1 = – line DESCRIPTION 43 Product specification SAA7104E; SAA7105E ...
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... Table 88 Subaddresses A2H to A4H DATA BYTE BCY, BCU luminance and colour difference portion of border colour in underscan area and BCV 2004 Mar 04 SAA7104E; SAA7105E DESCRIPTION number of output pixels ------------------------------------------------------------- - line XINC = ------------------------------------------------------------- - number of input pixels ...
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... HLC4 HLC3 HLT1 HLT0 0 DESCRIPTION DESCRIPTION HLP11 HLP10 0 HLP31 HLP30 0 HLP51 HLP50 0 HLP71 HLP70 0 DESCRIPTION 45 Product specification SAA7104E; SAA7105E 1 with the HLC2 HLC1 HLC0 0 HLC9 HLC8 1. It consists HLP02 HLP01 HLP00 HLP22 HLP21 HLP20 HLP42 HLP41 HLP40 HLP62 HLP61 HLP60 ...
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... HPV11 HPV10 HPD25 HPD24 HPV21 HPV20 HPD35 HPD34 HPV31 HPV30 DESCRIPTION DESCRIPTION HPVE5 HPVE4 DESCRIPTION DESCRIPTION DESCRIPTION 46 Product specification SAA7104E; SAA7105E HPD03 HPD02 HPD01 0 0 HPD09 HPD13 HPD12 HPD11 0 0 HPD19 HPD23 HPD22 HPD21 0 0 HPD29 HPD33 HPD32 HPD31 ...
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... RED, GREEN and BLUE portion of auxiliary cursor colour and AUXB Table 105 Subaddresses F9H and FAH DATA BYTE XCP horizontal cursor position Table 106 Subaddress FAH DATA BYTE XHS horizontal hot spot of cursor 2004 Mar 04 SAA7104E; SAA7105E DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 47 Product specification ...
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... In subaddresses 5BH, 5CH, 5DH, 5EH, 62H and D3H all IRE values are rounded up. 2004 Mar 04 DESCRIPTION DESCRIPTION DESCRIPTION -Y-C matrix is active R B -Y-C matrix is bypassed R B DESCRIPTION DESCRIPTION 48 Product specification SAA7104E; SAA7105E -Y -Y -Y-C (ITU-R BT.656, 27 MHz clock -Y-C (special bit ordering ...
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... O_E 1 during even field 0 during odd field Table 114 Subaddress 1CH DATA BYTE CID chip ID of SAA7104E = 04H; chip ID of SAA7105E = 05H Table 115 Subaddress 80H LOGIC DATA BYTE LEVEL IFERR 0 normal FIFO state 1 input FIFO overflow/underflow has occurred ...
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... SCBW = 1. (2) SCBW = 0. handbook, halfpage (1) SCBW = 1. (2) SCBW = 0. 2004 Mar 04 ( Fig.4 Chrominance transfer characteristic (dB) 0 (1) ( 0.4 0.8 1.2 Fig.5 Chrominance transfer characteristic 2. 50 Product specification SAA7104E; SAA7105E MBE737 (MHz) MBE735 1.6 f (MHz) 14 ...
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... CCRS1 = 0; CCRS0 = 0. Fig.6 Luminance transfer characteristic 1 (excluding scaler). handbook, halfpage (1) CCRS1 = 0; CCRS0 = 0 Fig.7 Luminance transfer characteristic 2 (excluding scaler). 2004 Mar 04 (4) (2) (3) ( (dB) ( Product specification SAA7104E; SAA7105E (MHz) MBE736 6 f (MHz) MGD672 14 ...
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... Fig.8 Luminance transfer characteristic in RGB (excluding scaler). handbook, full pagewidth (dB Fig.9 Colour difference transfer characteristic in RGB (excluding scaler). 2004 Mar Product specification SAA7104E; SAA7105E MGB708 (MHz) MGB706 (MHz) ...
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... The 5 special pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO). Table 116 BST instructions supported by the SAA7104E; SAA7105E INSTRUCTION BYPASS This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO when no test operation of the component is required ...
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... SAA7105E. Fig.10 32 bits of identification code. CONDITIONS outputs in 3-state outputs in 3-state; note 1 and V SSA(n) SSD(n) human body model; note 2 machine model; note 3 DDD 54 Product specification SAA7104E; SAA7105E LSB 1 0 TDO 1 MHC568 LSB 1 0 TDO 1 MHC569 MIN. MAX. UNIT 0.5 +4 ...
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... An ample copper area direct under the SAA7104E; SAA7105E with a number of through-hole plating, which connect to the ground layer (four-layer board: second layer), can also reduce the effective R addition the usage of soldering glue with a high thermal conductance after curing is recommended. ...
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... PD11 to PD0 2 pins PD11 to PD0 0.9 pins HSVGC, VSVGC 2 and FSVGC; note 6 pins HSVGC, VSVGC 1.5 and FSVGC; note 6 note Product specification SAA7104E; SAA7105E TYP. MAX. UNIT 0.1 V 0.4 V 0 DDD1 V V DDD1 V V DDD2 0.3V ...
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... FSVGC and CBO pins TDO, 3 TTXRQ_XCLKO2, VSM and HSM_CSYNC pins TDO, TTXRQ_XCLKO2, VSM and HSM_CSYNC see Table 117 see Table 117 see Table 117 see Table 117 3 dB; note 8 57 Product specification SAA7104E; SAA7105E TYP. MAX. UNIT 1.5 1.8 fF 3.5 4 ...
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... Mar 100 mV for LOW. 2 DDD2 is generated on chip. = 37.5 and (typical). L ext T PIXCLK t HIGH HD;DAT t HD;DAT t SU;DAT t o(d) t o(h) Fig.11 Input/output timing specification. 58 Product specification SAA7104E; SAA7105E V OH 0.5V DDD1 0.5V DDD1 SU;DAT MHC567 ...
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... Philips Semiconductors Digital video encoder handbook, full pagewidth HSVGC CBO PD handbook, full pagewidth HSVGC VSVGC CBO 2004 Mar 04 XOFS IDEL XPIX HLEN Fig.12 Horizontal input timing. YOFS YPIX Fig.13 Vertical input timing. 59 Product specification SAA7104E; SAA7105E MHB905 MHB906 ...
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... It is essential to note that the two pins used for teletext insertion must be configured for this purpose by the 2 correct Fig.14 Teletext timing. 60 Product specification SAA7104E; SAA7105E is the internally used insertion window for C-bus register settings. t i(TTXW MHB891 24 ...
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... H 27 MHz XTALI XTALO SAA7104E SAA7105E V SSA RSET 1 k AGND AGND Fig.15 Application circuit. 61 Product specification SAA7104E; SAA7105E 0.1 F AGND use one capacitor for each V DDA V DDA1 to V DDA3 VSM, HSM_CSYNC GREEN_VBS_CVBS FLTR0 75 75 AGND AGND AGND RED_CR_C_CVBS FLTR1 ...
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... Philips Semiconductors Digital video encoder handbook, halfpage 2004 Mar 04 C16 120 2.7 H 2.7 H C10 C13 390 pF 560 pF AGND JP11 JP12 FIN FILTER 1 = byp. ll act. Fig.16 FLTR0, FLTR1 and FLTR2 of Fig.15. 62 Product specification SAA7104E; SAA7105E FOUT MHB912 ...
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... R can be placed in series with the oscillator output XTALO. s Note: The decreased crystal amplitude results in a lower drive level but on the other hand the jitter performance will decrease. Fig.17 Oscillator application. 63 Product specification SAA7104E; SAA7105E SAA7104E SAA7105E A6 XTALO 27.00 MHz 39 39 ...
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... Mar 04 SAA7104E; SAA7105E Tables for example a standard PAL or NTSC signal) conditions occupy different conversion ranges, as indicated in Table 117 for a By setting the reference currents of the DACs as shown in Table 117, standard compliant amplitudes can be achieved for all signal combinations ...
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... 1 1 scale 13.7 15.2 13 0.3 13.0 14.8 13.0 REFERENCES JEDEC JEITA MS-034 - - - 65 Product specification SAA7104E; SAA7105E SOT472 detail 0.15 0.35 0.1 EUROPEAN ISSUE DATE PROJECTION 00-03-04 03-01-22 ...
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... Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 66 Product specification SAA7104E; SAA7105E ...
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... The appropriate soldering profile can be provided on request. 9. Hot bar or manual soldering is suitable for PMFP packages. 2004 Mar 04 (1) (3) , TFBGA, not suitable not suitable suitable not recommended not recommended (8) not suitable 67 Product specification SAA7104E; SAA7105E SOLDERING METHOD (2) WAVE REFLOW suitable (4) suitable suitable (5)(6) suitable (7) suitable not suitable ...
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... Product specification SAA7104E; SAA7105E DEFINITION These products are not Philips Semiconductors ...
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... Philips. This specification can be ordered using the code 9398 393 40011. 2004 Mar components conveys a license under the Philips’ system provided the system conforms to the I 69 Product specification SAA7104E; SAA7105E 2 C patent to use the 2 C specification defined by ...
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Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited ...