QT2032-EKG-1A2 Applied Micro Circuits Corporation, QT2032-EKG-1A2 Datasheet - Page 86

• Manufacturer Part Number: QT2032-EKG-1A2
• Manufacturer: Applied Micro Circuits Corporation

Specifications of QT2032-EKG-1A2

• Lead Free Status / RoHS Status: Supplier Unconfirmed

QT2022/32 - Data Sheet: DS3051
10.5.2 rx_flag and tx_flag DOM Alarm Fields
rx_flag and tx_flag alarm signals will be generated by the QT2022/32 using information read from MDIO DOM
diagnostic alarm registers 1.A070h and 1.A071h and MDIO NVR diagnostic alarm enable registers, 1.9006h and
1.9007h. The default state for registers 1.9006h and 1.9007h is 0.
rx_flag is placed in bit 1 of the MDIO RX_ALARM register, 1.9003h.1. tx_flag is placed in bit 1 of the MDIO
TX_ALARM register, 1.9004h.1. These register bits are latched when high and cleared on read. The RX_ALARM
register values, 1.9003h.0:15, along with their corresponding enable bits, 1.9000h.0:15, are used to create the
rx_alarm signal. The TX_ALARM register values, 1.9004h.0:15, along with their corresponding enable bits,
1.9001h.0:15, are used to create the tx_alarm signal.
The default value for the tx_flag alarm enable register, 1.9001h.1, will be 0. The default value for the rx_flag alarm
enable register, 1.9000h.1, will be 0.
QT2022/32 will generate the LASI signal.
Since the 1.A071h and 1.A070h registers are read only registers, a diagnostic alarm condition will not be cleared
until the DOM registers are updated with alarm free information followed by a read of RX and TX ALARM latched
high registers to clear them.
10.5.3 DOM Updates
The DOM register update rate will be set by MDIO DOM register 1.A100h.1:0 contents. Writing 00 to these bits will
initiate a single upload of the DOM registers. If these bits are set to any other state the DOM registers be periodi-
cally updated.
Table 35: DOM Update Rates
The EEPROM bus protocol transmits bit 7 first. EEPROM/DOM bits are numbered from 0 to 7. EEPROM/DOM bit
0 is mapped to MDIO register bit 0, EEPROM/DOM bit 7 is mapped to MDIO register bit 7. The upper 8 MDIO reg-
ister bits are hard wired to 0.
If a DOM update is requested while a NVR register read or write is in progress, the NVR transaction will be allowed
to complete and the DOM update will begin when the NVR transaction completes. While the DOM update is waiting
to happen the DOM command register will indicate a transaction in progress. The same applies if an NVR transac-
tion is requested while a DOM update is in progress. While an NVR or DOM update is queued, the associated
command register will be put in the command in progress state.
For a single update of the DOM registers the command status register, 1.A100h, functions the same way as the
NVR command status register - see XENPAK MSA Figure 19.
86
A100h.1:0
00
01
10
11
rx_flag = {OR of (reg 1.A071h.n ‘bit wise AND’ reg 1.9007.n) for n=0 to 7}
tx_flag = {OR of (reg 1.A070h.n ‘bit wise AND’ reg 1.9006.n) for n=0 to 7}
tx_alarm = {OR of (reg 1.9004.n ‘bit wise AND’ reg 1.9001.n) for n=0 to 9}
rx_alarm = {OR of (reg 1.9003.n ‘bit wise AND’ reg 1.9000.n) for n=0 to 5}
write of 00 initiates a single update of MDIO DOM registers
periodic update of MDIO DOM registers every 60 seconds
periodic update of MDIO DOM registers every 10 seconds
periodic update of MDIO DOM registers every 1 second
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