QT2032-EKG-1A2 Applied Micro Circuits Corporation, QT2032-EKG-1A2 Datasheet - Page 60

• Manufacturer Part Number: QT2032-EKG-1A2
• Manufacturer: Applied Micro Circuits Corporation

Specifications of QT2032-EKG-1A2

• Lead Free Status / RoHS Status: Supplier Unconfirmed

QT2022/32 - Data Sheet: DS3051
8.3.2 SONET Clock Rate Control Pin (REFSEL622)
The QT2032 can accept a 155.52 MHz or 622.08 MHz reference clock on the SREFCLK input. This control pin is
used to select the SONET input clock rate expected by the chip. When REFSEL622 is low, the chip expects a
155.52 MHz clock. When it is high, the chip expects a 622.08 MHz clock. The input uses 1.2V logic but is compati-
ble with 3.3V logic.
The input has an 50k Ω internal pulldown, so the default expected clock rate is 155.52 MHz if the input is not
connected.
8.3.3 VCXO Clock Rate Control Pin (VCXOSEL622)
The QT2032 can accept a 155.52 MHz or 622.08 MHz reference clock on the VCXO input. This control pin is used
to select the clock rate expected by the chip. When VXCOSEL622 is low, the chip expects a 155.52 MHz clock.
When it is high, the chip expects a 622.08 MHz clock. The input uses 1.2V logic but is compatible with 3.3V logic.
The input has an 50k Ω internal pulldown, so the default expected clock rate is 155.52 MHz if the input is not
connected.
8.3.4 VCXOB Control Pin
The QT2032 provides support for a VCXO-based PLL to filter phase noise on the SREFCLK or fiber RX recovered
clock to ensure compliant jitter generation and jitter transfer performance on the TX Fiber Output. The VCXOB pin
is used to control the VCXO PLL.
When the VCXOB pin is high, the external VCXO PLL will not be used and the input signals on the VCXOIP/N pins
will be ignored. When VXCOB is low, the external VCXO PLL is enabled and the input signals on the VCXOIP/N
will be used to time the TX PLL.
The input has an 50k Ω internal pullup, so the default configuration of the VCXOB pin is to disable the VXCO PLL if
the pin is not connected.
8.3.5 VXCOONLY Control Pin
In a linetiming application where an external VXCO PLL has been implemented, the VXCOONLY control pin is
pulled high to indicate that no clock has been provided at the SREFCLK input. When VXCOONLY is pulled low, the
clock recovery circuitry will expect a valid SREFCLK. When a valid RX recovered clock is present (indicated by the
LTIMEOK pin), the VXCO PLL will function normally.
When operating in VCXOONLY mode (VXCOONLY=1), set REFSEL622 = VCXOSEL622 for proper operation.
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