QT2032-EKG-1A2 Applied Micro Circuits Corporation, QT2032-EKG-1A2 Datasheet - Page 41

• Manufacturer Part Number: QT2032-EKG-1A2
• Manufacturer: Applied Micro Circuits Corporation

Specifications of QT2032-EKG-1A2

• Lead Free Status / RoHS Status: Supplier Unconfirmed

The Synchronization process accepts data from the PMA (via the PMA Service Interface, depicted as rx_data-
group<15:0> in Figure 11) and performs an alignment operation to delineate both octet and frame boundaries
within the received data stream. Aligned and framed data is passed to the WIS Receive process (depicted as
sync_bits<15:0> in Figure 11), where Section and Line Overhead octets are extracted from the WIS frames and
processed after descrambling the frame data. The payload pointer within the Line Overhead is used to delineate
the start and end of received SPE, and the Path Overhead is extracted from the SPE and processed. Finally, the
fixed stuff is removed from the SPE and the resulting data stream is conveyed to the PCS via the WIS Service
Interface (depicted as rx_data-unit<15:0>).
7.2.1 WIS Synchronization (Octet and Frame Delineation)
The WIS Synchronization process delineates both octet and WIS frame boundaries in the received signal. Delinea-
tion of these boundaries and alignment of the received data are done prior to performing the descrambling
function. (The SPE delineation process is done after descrambling the received data.)
The WIS Synchronization process monitors the last 64 A1 octets and the first 64 A2 octets in the Section Over-
head, forming the synchronization pattern. WIS Sync is achieved after 4 frames with valid synchronization patterns
are received. A loss of WIS synchronization (WIS Loss of Sync) is triggered when any bit errors are detected within
the synchronization pattern for 4 consecutive frames. When the WIS receiver is not in the Sync state all other WIS
processes are suspended. This includes all further alarm processing, including SEF and LOF alarms. The WIS
Synchronization process follows the state diagrams detailed in IEEE 802.3-2005 Figures 50-15 and 50-16.
A loss of WIS synchronization is reported by the chip as a WIS Local Fault in MDIO register bit 2.1.7. It is also
linked to LASI alarm bit 1.9003h.9. The parameter values for the WIS Synchronization state diagram are listed in
Table 12 on page 41.
Table 12: WIS Synchronization Process Parameters
7.2.2 SEF Defect Generation
The device monitors for an SEF defect by checking all 192 A1 and A2 octets in the Section Overhead. This is a
separate monitoring process from WIS Synchronization and uses a larger framing pattern. An SEF defect is raised
when any bit errors are detected within the framing pattern for 5 consecutive frames. An SEF defect is terminated
when two contiguous error-free frame words are detected.
The SEF framing pattern is a superset of the WIS Synchronization framing pattern. If bit errors are detected within
the WIS Synchronization framing pattern, a WIS Loss of Sync alarm will be raised after 4 frames. In this case an
SEF defect will not be raised. If bit errors are detected in the wider SEF framing pattern then an SEF defect will be
raised but a WIS Loss of Sync alarm will not.
1. Consult the Errata for additional details.
Revision 5.11
Parameter
m
k
n
f
i
j
AppliedMicro - Confidential & Proprietary
Value
128
64
64
64
4
4
1
Controls width of Sync_Pattern pattern
Controls width of Hunt_Pattern pattern
Controls width of Presync_Pattern pattern
Controls width of Presync_Pattern pattern
Controls hysteresis for SYNC state entry
Controls hysteresis for SYNC state exit
Purpose
QT2022/32 - Data Sheet: DS3051
41