QT2032-EKG-1A2 Applied Micro Circuits Corporation, QT2032-EKG-1A2 Datasheet - Page 35

• Manufacturer Part Number: QT2032-EKG-1A2
• Manufacturer: Applied Micro Circuits Corporation

Specifications of QT2032-EKG-1A2

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.3 TXPLLOUT Output Clock Driver
A clock from the transmit PLL can be output at pins TXPLLOUTP/N to serve as a reference clock to the XFP mod-
ule in an XFP host board application or for test purposes. The output driver is a CML type.
In XFP mode (XFP=1), the output driver is enabled by default and can be disabled by setting 1.C001h.3=1. In non-
XFP mode (XFP=0), the output driver is disabled by default and can be enabled by setting 1.C001h.3=1. The driver
is also automatically disabled when 1.C001h.7=1 to allow the TXPLLOUTP/N pins to serve as the input for a sec-
ond reference source in a multi-rate module. The TXPLLOUT control logic is detailed in figure 7 on page 35.
Table 7:
For the QT2032, the frequency of TXPLLOUTP/N depends on several pin settings as shown in Table 8. For the
QT2022, the frequency is solely determined by the XFP pin (shown in bold text).
Table 8:
1.
2.
Revision 5.11
0
0
0
0
1
1
0
0
0
0
0
The indicated polarity of the XFP input can be reversed by asserting bit 1.C001h.2.
SONET = bit_2.7.0 AND not(LANMODE).
TXPLLOUT Driver Control and LAN Reference Selection
TXPLLOUT Output Frequency vs TXOUT Baud-rate
X
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
x
X
X
0
1
X
X
AppliedMicro - Confidential & Proprietary
Inputs
X
X
X
X
0
1
divide by...
0
1
0
1
x
64
64
16
64
16
66
note
(CMOS source, results in higher jitter in this mode)
(CML source, results in lower jitter in this mode)
(CML source, results in lower jitter in this mode)
(CML source, results in lower jitter in this mode)
(CML source, results in lower jitter in this mode)
(CML source, results in lower jitter in this mode)
OFF
ON
ON
OFF
OFF
QT2022/32 - Data Sheet: DS3051
State
EREFCLK
EREFCLK
EREFCLK
EREFCLK
TXPLLOUT
35