QT2032-EKG-1A2 Applied Micro Circuits Corporation, QT2032-EKG-1A2 Datasheet - Page 29

• Manufacturer Part Number: QT2032-EKG-1A2
• Manufacturer: Applied Micro Circuits Corporation

Specifications of QT2032-EKG-1A2

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Figure 7:
The TX Fiber Output derives timing either from a 155.52 MHz or 622.08 MHz reference applied at SREFCLK (or
VCXOI when in VCXOONLY mode) or the received signal on the RX Fiber Input. The TX PLL generates a 10 GHz
clock from the selected reference by multiplying the frequency. The TX PLL output provides timing for the TX Fiber
Processing Block and Output. By default the TX PLL will lock to the reference applied at SREFCLK (or VCXOI
when in VCXOONLY mode), however it may optionally lock to the recovered clock from the RX Fiber CDR as
explained in Section 6.2.2 on page 30. In order to reduce phase noise from the selected reference and conse-
quently on the TX Fiber Output, an optional VCXO PLL may be used to filter phase noise on the selected
reference, as explained in Section on page 32.
The RX Fiber CDR locks to the received signal and generates a recovered clock. The recovered clock provides a
clock to the RX Fiber Processing Block and provides an optional reference for the TX Fiber Output. When the
recovered clock deviates by >500ppm from the reference clock, the RX Fiber Input CDR will then lock to the refer-
ence from SREFCLK (or VCXOI when in VCXOONLY mode) to pull the VCO frequency to nominal frequency. The
CDR will lock to the RX Fiber Input signal when the clock rate is <500ppm from the reference.
The RX XAUI Outputs derive timing from a 156.25 MHz reference applied at EREFCLK. The RX PLL generates the
3.125 GHz reference from the reference by multiplying the frequency. The RX PLL output provides a clock for the
RX XAUI Processing Block and Outputs.
For each TX XAUI Input, a CDR locks to the received signal and generates a recovered clock. The recovered clock
from lane 1 (TxXAUI1) provides timing to the TX XAUI Processing Block.
Transfer of data across clock boundaries along each data path is accomplished through rate compensation blocks.
Revision 5.11
Interface
Interface
RxXAUI2P/N
RxXAUI2P/N
RxXAUI1P/N
RxXAUI1P/N
RxXAUI2P/N
RxXAUI2P/N
RxXAUI3P/N
RxXAUI3P/N
TxXAUI0P/N
TxXAUI0P/N
TxXAUI1P/N
TxXAUI1P/N
TxXAUI2P/N
TxXAUI2P/N
TxXAUI3P/N
TxXAUI3P/N
XAUI
XAUI
RX XAUI
RX XAUI
TX XAUI
TX XAUI
Outputs
Outputs
Inputs
Inputs
WAN Mode Timing without Fixed Frequency Reference
EREFCLK
EREFCLK
156.25 MHz
156.25 MHz
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
PLL
PLL
RX
RX
XO
XO
AppliedMicro - Confidential & Proprietary
Processing
Processing
Processing
Processing
TX XAUI
TX XAUI
RX XAUI
RX XAUI
Coarse control voltage
Coarse control voltage
used to center CDR VCO
used to center CDR VCO
tuning range.
tuning range.
RX Data Path
RX Data Path
TX Data Path
TX Data Path
Com pensation
Com pensation
Com pensation
Com pensation
Rate
Rate
Rate
Rate
Processing
Processing
Processing
Processing
TX Fiber
TX Fiber
RX Fiber
RX Fiber
TXPLLOUT
TXPLLOUT
TXPLLOUT
PLL
PLL
TX
TX
SREFCLK
SREFCLK
VCXO
VCXO
QT2022/32 - Data Sheet: DS3051
PLL
PLL
CDR
CDR
RX
RX
Coarse Control Voltage
Coarse Control Voltage
TX Fiber Output
TX Fiber Output
VCXO PLL includes
VCXO PLL includes
external VCXO , opamp,
external VCXO , opamp,
and filter components.
and filter components.
TX Fiber Input
TX Fiber Input
RX Fiber Recovered Clock
RX Fiber Recovered Clock
used for line timing.
used for line timing.
Tim ing Path
Tim ing Path
TXOUTP/N
TXOUTP/N
Fiber Interface
Fiber Interface
R XIP/N
R XIP/N
VCXO output used to
VCXO output used to
center CDR VCO when
center CDR VCO when
input signal is failed.
input signal is failed.
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