QT2032-EKG-1A2 Applied Micro Circuits Corporation, QT2032-EKG-1A2 Datasheet - Page 26

• Manufacturer Part Number: QT2032-EKG-1A2
• Manufacturer: Applied Micro Circuits Corporation

Specifications of QT2032-EKG-1A2

• Lead Free Status / RoHS Status: Supplier Unconfirmed

QT2022/32 - Data Sheet: DS3051
5.2.10 8B/10B Encoder
The data bus is divided into four 8-bit wide data channels. Each of the four channels has independent 8B/10B
encoders which will convert the 8 bit data lanes into 10 bit code words. Either a positive or negative disparity 10 bit
code word will be selected, depending on the running disparity.
5.2.11 Receive Multiplexer and XAUI Interface
After 8b/10b encoding has been added, the receive multiplexer serializes data words to form four 3.125Gb/s output
data lanes.The XAUI output drivers provide low-swing differential outputs with 100 Ω differential output impedance
and are intended to be AC coupled. The 3.125 GHz timing is derived from the reference clock, EREFCLK.
6 Datapath Clocking
This section explains the clocking architecture and features of the QT2022 & QT2032.
6.1 LAN Application Timing Modes (QT2022 and QT2032)
6.1.1 Timing Architecture in LAN Mode
This section describes the timing of the QT2022. The QT2032 will follow this timing architecture when placed in
LAN mode.
In LAN mode, the RxXAUI and TX Fiber quadrants share timing references, but are generally independent of the
TxXAUI and RX Fiber quadrants. The timing architecture and timing paths in LAN mode are illustrated in Figure 5.
Figure 5:
26
RxXAUI2P/N
RxXAUI2P/N
RxXAUI1P/N
RxXAUI1P/N
RxXAUI2P/N
RxXAUI2P/N
RxXAUI3P/N
RxXAUI3P/N
TxXAUI0P/N
TxXAUI0P/N
TxXAUI1P/N
TxXAUI1P/N
TxXAUI2P/N
TxXAUI2P/N
TxXAUI3P/N
TxXAUI3P/N
Interface
Interface
RX XAUI
RX XAUI
TX XAUI
TX XAUI
Outputs
Outputs
Inputs
Inputs
XAUI
XAUI
LAN Mode Timing (QT2022 and QT2032)
CDR
CDR
CDR
CDR
CDR
CDR
CDR
CDR
PLL
PLL
RX
RX
AppliedMicro - Confidential & Proprietary
Processing
Processing
Processing
Processing
TX XAUI
TX XAUI
RX XAUI
RX XAUI
Coarse control voltage
Coarse control voltage
used to center CDR VCO
used to center CDR VCO
tuning range.
tuning range.
TX Data Path
TX Data Path
RX Data Path
RX Data Path
Compensation
Compensation
Compensation
Compensation
Rate
Rate
Rate
Rate
Processing
Processing
Processing
Processing
RX Fiber
RX Fiber
TX Fiber
TX Fiber
EREFCLK
EREFCLK
156.25 MHz
156.25 MHz
PLL
PLL
TX
TX
XO
XO
Alternate
Alternate
XO
XO
CDR
CDR
RX
RX
TXPLLOUT
TXPLLOUT
Coarse Control Voltage
Coarse Control Voltage
SREFCLK
SREFCLK
TX Fiber Output
TX Fiber Output
Fiber Interface
Fiber Interface
RX Fiber Recovered Clock
RX Fiber Recovered Clock
may be used as timing
may be used as timing
reference. Test mode only.
reference. Test mode only.
TX Fiber Input
TX Fiber Input
Reference used to center
Reference used to center
CDR VCO when TX Fiber
CDR VCO when TX Fiber
Input signal is failed.
Input signal is failed.
Timing Path
Timing Path
TXOUTP/N
TXOUTP/N
RXIP/N
RXIP/N
Revision 5.11