QT2032-EKG-1A2 Applied Micro Circuits Corporation, QT2032-EKG-1A2 Datasheet - Page 171

• Manufacturer Part Number: QT2032-EKG-1A2
• Manufacturer: Applied Micro Circuits Corporation

Specifications of QT2032-EKG-1A2

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Revision 5.11
15:0
0
1
2
3
4
5
6
7
15:8
1. Both
Bit
Bit
Checkers On == (3.C020h.0=1) OR (3.C020h.1=1) OR (3.C030h.0=1) OR (3.C020h.0=1)
TX Packet Checker Enable
RW
0 = Disable, Default
1 = Enable
RX Packet Checker Enable
RW
0 = Disable, Default
1 = Enable
Reserved, RO
Reserved, RO
Packet Type, RW
00 = Data (fixed)
01 = Data (incremental)
10 = Control (fixed)
11 = Reserved
Default = 00
Reserved, RO
Reserved, RO
Reserved, RO
PCS Vendor Specific
Burst Size, RW
Default = 16’d256
Packet Checker
3.C030h
PCS Vendor Specific
Control
Packet Generator
Burst Size
3.C024h
1
AppliedMicro - Confidential & Proprietary
1
,
,
Lane 2 XGMII Data Byte, RW
Default = 8’h00
Lane 3 XGMII Data Byte, RW
Default = 8’h00
PCS Vendor Specific
Expected Data MSB
Packet Checker
Packet Size defined by XGMII columns,
RW
Default = 16’d5
3.C031h
PCS Vendor Specific
Packet Generator
Packet Size
3.C025h
Lane 0 XGMII Data Byte, RW
Default = 8’h00
Lane 1 XGMII Data Byte, RW
Default = 8’h00
PCS Vendor Specific
Expected Data LSB
Packet Checker
3.C032h
QT2022/32 - Data Sheet: DS3051
IPG Size defined by XGMII columns,
RW
Default = 16’d1
PCS Vendor Specific
Packet Generator
Lane 0 XGMII Control
Bit, RW
0 = Data, Default
1 = Control
Lane 1 XGMII Control
Bit, RW
0 = Data, Default
1 = Control
Lane 2 XGMII Control
Bit, RW
0 = Data, Default
1 = Control
Lane 3 XGMII Control
Bit, RW
0 = Data, Default
1 = Control
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
Reserved, RO
PCS Vendor Specific
IPG Size
3.C026h
Expected Control
Packet Checker
3.C033h
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