QT2032-EKG-1A2 Applied Micro Circuits Corporation, QT2032-EKG-1A2 Datasheet - Page 215

• Manufacturer Part Number: QT2032-EKG-1A2
• Manufacturer: Applied Micro Circuits Corporation

Specifications of QT2032-EKG-1A2

• Lead Free Status / RoHS Status: Supplier Unconfirmed

18.8 XAUI Traffic Testing with a BERT
It is possible to program a parallel traffic generator and error detector (BERT) to generate and detect errors in a
XAUI-compliant data stream. For example, the exact CJPAT pattern can be programmed into the BERT’s pattern
buffer, as specified in IEEE 802.3-2005 Clause 48A.5.1. This pattern can be sent into the XAUI input of a QT2022/
32 device, looped back on the fiber interface and returned to the BERT error detector. In this setup, the QT2022/32
LAN reference clock must be synchronous to the BERT reference clock. This test setup is shown in Figure 18.8.
During normal operation of the QT2022/32, this test setup will fail to work as intended. The BERT error detector will
not be able to synchronize to the output data from the DUT. This is due to the idle randomization process in the 8b/
10b encoder, which will scramble the ||A||, ||K|| and ||R|| codes in the signal stream. The bitstream received by the
BERT will not exactly match the transmitted bitstream. Since the BERT is not protocol-aware, it will be unable to
synchronize to this pattern.
This problem can be defeated by disabling the idle decode process within the QT2022/32.
Figure 62: XAUI Pattern Testing with a Parallel BERT
This is described in detail in Section 11.7, “Disabling the Idle Decode Process,” on page 106. When the idle decode
process has been disabled, the test setup in Figure 18.8 will work as expected. However, the disparity of the output
signal from the QT2022/32 must be accounted for in the BERT receiver pattern.
18.8.1 Running Disparity with CJPAT
The CJPAT pattern produces the same disparity on all 4 lanes. Only two possible encodings can occur. Only one of
the two encodings will match the signal from the RxXAUI output from the chip. Each pattern must be loaded into
the BERT’s pattern buffer to see which one matches. The running disparity will be maintained until the signal is
interrupted.
If the signal is interrupted or the chip is reset, the running disparity will have a 50:50 chance of remaining the same.
The CJPAT pattern that is loaded into the BERT might need to be swapped for the alternate pattern.
Note: The CJPAT pattern cited in the IEEE 802.3-2005 Standard Clause 48A.5.1 does not include sufficient idle
codes to meet the input requirements of the XAUI interface. These requirements are specified in Clause 48.2.4.2.
More specifically, Lane 0 does not receive a valid ||A|| ordered_set to allow lane alignment (see Table 48A-10). In
order for the CJPAT pattern to work properly, an additional ||A|| column must be added at the end of the pattern.
Revision 5.11
CLOCK SOURCE
3.125GHz
Parallel BERT
AppliedMicro - Confidential & Proprietary
EXTERNAL
SYNC
XAUI
CLOCK SOURCE
QT2032/
QT2022
PHY
156.25MHz
PHYSICAL
MEDIUM
QT2022/32 - Data Sheet: DS3051
DATA
CLOCK
215