QT2032-EKG-1A2 Applied Micro Circuits Corporation, QT2032-EKG-1A2 Datasheet
QT2032-EKG-1A2
Specifications of QT2032-EKG-1A2
QT2032-EKG-1A2 Summary of contents
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... Gb/s Serial-to-XAUI PHY ICs for Ethernet and Fibre Channel LAN/ 1 Description The QT2032 and QT2022 products are fully integrated PHY ICs designed for use in 10 Gb/s IEEE 802.3-2005 compliant Ethernet and Fibre Channel LAN, SAN and WAN applications. The main physical layer functions (PHY) of the receiver and transmitter are integrated onto a single chip ...
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... XAUI Interface Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.3 PCS Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.4 Serial Interface Test Features 100 11.5 WIS Test Features (QT2032 only 102 11.6 Ethernet Packet Generator/Checker (QT2032 and QT2022 103 11.7 Disabling the Idle Decode Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 2 AppliedMicro - Confidential & Proprietary TABLE OF CONTENTS Revision 5 ...
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... Test Access Port and Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12 Extended Link Monitoring Feature (QT2032 and QT2022 109 12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 12.2 Query message format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.3 Messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 12.4 Extended Link Monitoring State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 12.5 Transmit State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 12.6 Receive State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12 ...
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... Bottom: Module application Figure 2: QT2022/32 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 3: Transmit Scrambler Figure 4: Receive Descrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 5: LAN Mode Timing (QT2022 and QT2032 Figure 6: WAN Mode Timing with Fixed Frequency Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 7: WAN Mode Timing without Fixed Frequency Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 8: Line Timing Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 9: VCXO PLL Interface Block Diagram ...
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Figure 41: Schematic Representation of Extended Link Monitoring Transaction Between Two PHYs . . . . . . . . 109 Figure 42: Extended Link Monitoring State Diagram . . . . . . . . . . . . ...
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... QT2022/32 - Data Sheet: DS3051 Table 1: QT2032 Ball Arrangement Top View (through the package .11 Table 2: QT2022 Ball Arrangement Top View (through the package Table 3: QT2022/32 Ball Assignment & Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4: Supply Pad and Ball Assignment and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 5: Line Timing Control Modes Table 6: VCXO PLL Control Pin Settings ...
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Table 42: PRBS31 Generator and Checker Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Optional ability to configure registers from an external EEPROM on powerup or reset Configurable polarity of low-speed CMOS I/O 25MHz MDIO operation 1. QT2032 only QT2032 WIS Features WIS interface with extended SONET overhead processing SONET overhead serial interface Line-timing capability with optional VCXO interface Conditional (auto-linetiming) or forced line-timing operation ...
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Features PLL lock indications Ability to override fault indications Characteristics Electrical Power supplies Power consumption, LAN applications Power consumption, WAN applications Mechanical Package Ball spacing Environmentally friendly package Revision 5.11 AppliedMicro - Confidential & Proprietary QT2022/32 - Data Sheet: DS3051 ...
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QT2022/32 - Data Sheet: DS3051 3 Available Package Options The body of the QT2022/32 package complies with the RoHS directive for elimination of banned materials. The sol- der balls are composed of a SnAgCu alloy, which requires a hotter thermal ...
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... Pin Assignment and Description 4.1 QT2032 Ball Arrangement The QT2032 comes in a 15x15 mm 2 LBGA package with 1.0 mm ball pitch. The pin arrangement is shown in Table 1 and the pin assignments are described in Table 3. Table 1: QT2032 Ball Arrangement Top View (through the package) ...
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... The QT2022 comes in a 15x15 mm 2 LBGA package with 1.0 mm ball pitch. The pin arrangement is shown in Table 2 and the pin assignments are described in Table 3. The pin assignment is shared with QT2032 except for 14 balls which are unused in the QT2022. No ball locations are moved. ...
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... LAN reference clock input for fiber-side TXPLL. 156.25 MHz (10GE) or 159.375 (10GFC) On chip 50Ω terminations to 1.2 V. Requires external AC coupling. QT2032: SONET reference clock input for fiber-side TXPLL in WAN-mode 155.52 MHz or 622.08 MHz selected by REFSEL622 pin; AC coupled with on chip 50Ω terminations to 1.2 V QT2022: Unused ...
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... M4 TXFN 14 AppliedMicro - Confidential & Proprietary Type QT2032: Input clock from VCXO when an external VCXO is used for the fiber side TXPLL reference clock input in WAN-mode; 155.52 MHz or 622.08 MHz selected by VCXOSEL622 pin; AC coupled with on chip 50Ω terminations to 1.2 V. QT2022: Unused. Leave unconnected. ...
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... Unused. Leave unconnected. QT2032: VCXO frequency selection 0 = 155.52 MHz (default 622.08 MHz QT2022: Unused. Leave unconnected. QT2032: VCXO control loop enable pin. A low-level configures the chip to implement a PLL using an external VCXO - see description in Section 6.2.4, “VCXO PLL,” on page 32 enabled 1 = disabled (default) QT2022: Unused ...
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QT2022/32 - Data Sheet: DS3051 Table 3: QT2022/32 Ball Assignment & Signal Description (Continued) Ball Signal Name Dir. C6 PHOFF_EN I CMOS with 50kΩ pulldown C2 LEGACY I CMOS with 50kΩ pulldown C13 RXIN_SEL I CMOS with 50kΩ pulldown C5 ...
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... SONET overhead data; timed from the RDCC_CLK clock output. Please see Section 7.3.8, “Transport Overhead Serial Interface,” on page 48. QT2022: Unused. Connect to GND. QT2032: Gapped clock used for timing RDCC output. Please see Section 7.3.8, “Transport Overhead Serial Interface,” on page 48. ...
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... I/O CMOS input or 10mA open drain output 18 AppliedMicro - Confidential & Proprietary Type QT2032: Gapped clock used for timing TDCC input. Please see Section 7.3.8, “Transport Overhead Serial Interface,” on page 48 QT2022: Unused. Connect to GND. Test data output (scan out when SCAN instruction written to TAP).) ...
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Table 3: QT2022/32 Ball Assignment & Signal Description (Continued) Ball Signal Name Dir. D4 LED2 I/O CMOS input with 50kΩ pullup to 1.2V, or 10mA open drain output D5 LED3 I/O CMOS input or 10mA open drain output Reserved pins ...
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QT2022/32 - Data Sheet: DS3051 Table 4: Supply Pad and Ball Assignment and Description Supply (#) TV1P2 (4) 1.2V Supply for transmit fiber side circuits GND (54) Ground TV1P2A (2) 1.2V Supply for transmit PLL RV1P2 (4) 1.2V Supply for ...
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... VXCOI Output WIS TXOUT Gearbox Mux TX Driver (QT2032 only) WIS AMCC PMA PMA PCS loopback system loopback network loopback (QT2032 only) loopback Frame WIS Sync Demux CDR RX (QT2032 only) limiting amp freq LOS RXPLLOUT mon detector MDIO MDIO Control sync_err LOSOUTB ...
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... Proper rate compensation will always be performed when the clock rates are within 200ppm (total). The QT2022/ QT2032 can tolerate back-to-back 9600 byte jumbo frames with minimum IPG. If the clock rate difference exceeds 200ppm or multiple back-to-back jumbo frames are transmitted, one or more packets may be corrupted. ...
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... TXOUT_SEL high. 5.1.12 Line Timing Mode Line timing is used in the QT2032 to ensure the transmitted data is synchronized to the SONET network. In line timing mode, the reference clock used for the transmit PLL is derived from the recovered receive clock. Line timing mode is enabled by the Line Timing Control Register. Please see Section 6, “ ...
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... GHz recovered clock. The demultiplexer converts the 10 Gb/s serial incoming data into 64 parallel bits. A divide-by-64 recovered clock can be output at RXPLLOUT by setting MDIO register bit 1.C001h 5.2.5 Receive WAN Interface Sublayer (WIS) (QT2032 Only) The RX WIS block receives data from a SONET link and extracts the Ethernet payload from the STS-192c SPE. It also monitors the integrity of data at the Section, Line and Path levels and monitors both near and far end faults ...
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Frame Synchronization The frame synchronizer takes the 64 bit wide data bus output from the demultiplexer and converts bit wide data bus. The 66 bits are composed of 2 sync bits followed by 64 bits ...
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... LAN Application Timing Modes (QT2022 and QT2032) 6.1.1 Timing Architecture in LAN Mode This section describes the timing of the QT2022. The QT2032 will follow this timing architecture when placed in LAN mode. In LAN mode, the RxXAUI and TX Fiber quadrants share timing references, but are generally independent of the TxXAUI and RX Fiber quadrants ...
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... Line Timing Mode: Disabled, Automatic, or Forced, see Section 6.2.2 on page 30. In order to understand the relationship between timing reference and the behavior of input and output signals it is important to understand the general timing architecture of the QT2032. In the following sections, the timing archi- tecture in the WAN mode is explained. ...
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QT2022/32 - Data Sheet: DS3051 Figure 6: WAN Mode Timing with Fixed Frequency Reference TX XAUI TX XAUI Inputs Inputs TxXAUI0P/N TxXAUI0P/N CDR CDR TxXAUI1P/N TxXAUI1P/N CDR CDR TxXAUI2P/N TxXAUI2P/N CDR CDR TxXAUI3P/N TxXAUI3P/N CDR CDR XAUI XAUI RX RX ...
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Figure 7: WAN Mode Timing without Fixed Frequency Reference TX XAUI TX XAUI Inputs Inputs TxXAUI0P/N TxXAUI0P/N CDR CDR TxXAUI1P/N TxXAUI1P/N CDR CDR TxXAUI2P/N TxXAUI2P/N CDR CDR TxXAUI3P/N TxXAUI3P/N CDR CDR XAUI XAUI Interface Interface RX RX PLL PLL RxXAUI2P/N ...
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QT2022/32 - Data Sheet: DS3051 6.2.2 Line Timing Line timing permits the TX Fiber Output to derive timing from the RX Fiber Input. This mode is useful for applica- tions where it is necessary or desirable for the TX Fiber ...
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... The Automatic Line Timing mode allows the TX Fiber Output to derive timing from a valid recovered clock from the RX Fiber Input. When the RX Fiber Input is not valid, the TX Fiber Output derives timing from SREFCLK (or from VCXOI in VCXOONLY mode). The QT2032 deems the recovered clock from the RX Fiber Input to be valid when all of the following conditions are TRUE: 1 ...
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... The enable bit for each condition may be set as required by the implementation. 6.2.4 VCXO PLL As discussed in Section 6.2.1 on page 27, the QT2032 provides support for a VCXO based PLL to filter phase noise on the SREFCLK or recovered clock to ensure compliant jitter generation and jitter transfer performance as measured on the TX Fiber Output ...
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... VCXO PFD VCXOCTLN reference +400mV/0/-400mV REFSEL622 (logic) VCXOSEL622 VCXOONLY VCXOB frcvcxopfd = VCXOONLY AND !ltimeok LANMODE mdio_wis_en (MDIO 2.7.0) QT2022/32 - Data Sheet: DS3051 QT2032 Only VCXOB PLL refdvby4 refdvby4 = !VCXOSEL622 AND REFSEL622 AND !ltimeok vcxodvby4 = VCXOSEL622 AND !REFSEL622 AND !ltimeok ...
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... If no SREFCLK is implemented, and 20ppm operation for SONET applications is required, then the VCXO will likely need to be tem- perature-compensated. 6.2.6 VCXO Usage for QT2032 in LAN Mode Usage of an external VCXO is not supported in LAN mode. When a VCXO is implemented and the chip is switched to LAN mode, the VCXO must be disabled by setting pin VCXOB=1 ...
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... The TXPLLOUT control logic is detailed in figure 7 on page 35. Table 7: TXPLLOUT Driver Control and LAN Reference Selection Inputs For the QT2032, the frequency of TXPLLOUTP/N depends on several pin settings as shown in Table 8. For the QT2022, the frequency is solely determined by the XFP pin (shown in bold text). Table 8: TXPLLOUT Output Frequency vs TXOUT Baud-rate ...
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... This section describes the function and extended features of the WIS block in the QT2032. The WIS block is enabled and the chip will operate in WAN mode when LANMODE = 0. The WIS block can be bypassed by setting MDIO register 2.7 LANMODE = 1. When bypassed, the QT2032 will be 10GE (or 10GFC) protocol compliant. ...
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Path Overhead The main function of this overhead is to provide error monitoring and connectivity checks between Path Terminat- ing Equipment (PTE). Table 9: Path Overhead Definitions Overhead Octet Description J1 Path Trace B3 Path BIP-8 C2 STS Path ...
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QT2022/32 - Data Sheet: DS3051 7.1.3 Line Overhead The Line layer is responsible for the reliable transport of the Path layer payload and overhead. Line overhead is accessed where SPEs are multiplexed or protection switching is performed. Table 10: Line ...
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... Section Data Communication channel (DCC) 7.1.5 Test Pattern Generation The QT2032 provides WIS compliant test pattern generation features. Please refer to Section 11.5, “WIS Test Fea- tures (QT2032 only),” on page 102 for details. Revision 5.11 AppliedMicro - Confidential & Proprietary Value (Bits 1... 11110110 These bytes are allocated in each STS-1 for framing purposes ...
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QT2022/32 - Data Sheet: DS3051 7.2 WIS Receiver The WIS receiver functionality is illustrated in Figure 11. This is fully compliant with IEEE 802.3 Clause 50. There are additional extended features described in Section 7.3, “Extended WIS Features,” on page ...
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The Synchronization process accepts data from the PMA (via the PMA Service Interface, depicted as rx_data- group<15:0> in Figure 11) and performs an alignment operation to delineate both octet and frame boundaries within the received data stream. Aligned and framed ...
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QT2022/32 - Data Sheet: DS3051 7.2.3 LOF Defect Generation An LOF defect occurs when a Severely Errored Frame (SEF) persists for a period of 3 ms. The LOF defect is termi- nated when no SEF defects are detected for a ...
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Descrambler The descrambler processes the frame to reverse the effect of the scrambler using the same polynomial as scram- bler, with the exception of the A1,A2,J0 and Z0 octets (576 octets in total, per WIS frame), which bypass the ...
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... If the New Data Flag is set to 1001, then the coincident pointer value will replace the current one at the offset indicated by the new pointer value regardless of the state of the receive. The QT2032 receive pointer processor can react to any change in the pointer value, for example, the receiver can react to frame after frame of positive stuff, negative stuff. ...
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... The QT2032 implements the logic that detects when the far-end transmit side sends a pointer that does not follow the rules of pointer generation (ANSI- T1.105-1999 section 9.1.5 page 25). The Pointer process will also generate the LOP-P signal as follows: Either the logic received 8 consecutive frames with a pointer different than a valid pointer (active pointer) and none of the received pointer triggered: 1 ...
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... The QT2032 provides WIS compliant test pattern checking features. Please refer to Section 11.5, “WIS Test Fea- tures (QT2032 only),” on page 102 for details. 7.3 Extended WIS Features The QT2032 integrates a series of features common for SONET framer that are not supported by the WIS Clause. 46 AppliedMicro - Confidential & Proprietary ...
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... The SS bits in the STS-1 #1 transmit overhead can be programmed by the user. The SS bits are located in bits 5 and 6 of the H1 octet in the SONET overhead. This feature allows the QT2032 transmitted frame to be compatible with SDH networks, where the SS bits are typically set to ‘10’. For SONET networks, the default value of ‘00’ ...
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... Similarly, QT2032 has a 2 wire interface on the receive path for byte extraction: an output clock pin (RDCC_CLK) that runs at 155MHz / 80 and an output data pin (RDCC) is used to shift out the data (serial OH bytes). QT2032 will drive a new data value on the falling edge of the clock (the chip connected to the serial interface can safely latch 48 AppliedMicro - Confidential & ...
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... The gap in the clock can be used for synchronization purposes. In “D1-D12 mode”, QT2032 will kill/gate the clock for a minimum of 90 clock cycles, then drive the clock for 24 (3X8) clock cycles (D1-D3), then kill/gate the clock for a minimum of 48 clock cycles, then finally drive the clock for 72 (9x8) clock cycles (D4-D12) ...
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QT2022/32 - Data Sheet: DS3051 ified number of frames. The control bit initiates byte insertion for all 3 bytes simultaneously. It will only trigger byte insertion if a fixed number of frames is selected. To initiate insertion multiple times, toggle ...
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Internal Limitations The STS-1 overhead bytes are organized internally into groups of 8 bytes each. The STS-1 groups are [1..8], [9..16], [17..24] - [185..192]. For a given overhead byte within an STS-1, only one byte may be overwritten within a ...
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QT2022/32 - Data Sheet: DS3051 7.4 WIS Alarm Processing The WIS block detects defects on the fiber input and processes them. The defects are summarized in Table 14 below. Table 14: Summary of Defects Processed by WIS Defect/Anomaly Root Cause ...
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Local Fault Generation Certain errors on the fiber input prevent delineation of valid data from the incoming WIS frame. These errors include: Loss of WIS Synchronization, LOF, LOP-P, AIS-P and PLM-P. When any of these errors are detected, the ...
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... Control (Input) Pins (QT2022 and QT2032) The pins described in this section are common to both the QT2022 and QT2032. All pins have the same function for both products. The low speed control input pins are listed in Table 3, “QT2022/32 Ball Assignment & Signal Description,” on page 13 ...
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The following functions which are specifically for XENPAK EEPROMs are disabled in XFP mode: • EEPROM checksum • DOM capability • EEPROM_PROT protect capability • PMA/PMD type control through EEPROM • tx_flag and rx_flag for generating LASI ALARM • PMA/PMD ...
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QT2022/32 - Data Sheet: DS3051 8.2.7 Transmit Polarity Control Pin (TXOUT_SEL) TXOUT_SEL controls the 10 Gb/s transmit data output polarity as defined at the QT2022/32 pins/balls. The default setting, TXOUT_SEL=0, is compatible with XENPAK module requirements. Table 16: TXOUT Polarity ...
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XAUI Output Lane Ordering Control Pin (RxXAUI_SEL) RxXAUI_SEL controls the transmit path XAUI lane ordering as defined at the QT2022/32 pins/balls. The default setting, RxXAUI_SEL=0, is compatible with XENPAK module requirements. Table 18: RxXAUI Lane Ordering RxXAUI_SEL=0 RxXAUI3P RxXAUI3N ...
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QT2022/32 - Data Sheet: DS3051 8.2.13 Backwards Compatibility Control Pin (LEGACY) The LEGACY pin is used to revert several key register map definitions to be compatible with the AMCC QT2021 SerDes. When the LEGACY pin is low, the new QT2022/32 ...
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... Please see Table 3 for required connectivity information. 8.3.1 LAN Mode Control Pin (LANMODE) The LANMODE Control Pin is used to force the QT2032 into LAN mode. This pin is used in conjunction with the MDIO “Port Type Selection” bit (address 2.7.0). When LANMODE is low, the mode is determined by the “Port Type Selection” ...
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... VCXO Clock Rate Control Pin (VCXOSEL622) The QT2032 can accept a 155.52 MHz or 622.08 MHz reference clock on the VCXO input. This control pin is used to select the clock rate expected by the chip. When VXCOSEL622 is low, the chip expects a 155.52 MHz clock. ...
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... Low-Speed Output Pins (QT2022 and QT2032) The pins described in this section are common to both the QT2022 and QT2032. All pins have the same function for both products. All the low-speed output pins have the same type of open drain driver. An external 10-22 k Ω pullup resistor to 1 expected ...
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QT2022/32 - Data Sheet: DS3051 8.4.1 Link Alarm Status Interrupt Pin (LASI) The LASI pin is an active-low output used to indicate that a link fault condition has been detected in either the receive or transmit path. It can be ...
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... PHY_XS lane alignment (MDIO 4.24.12) When operating the QT2032 in WAN mode, additional WIS alarms can be programmed to assert LASI. These alarms are used to report a WIS-related link fault on the receive path. The block diagram for the WIS alarms is shown in Figure 18. The alarms feed into the RX_ALARM Status register shown in Figure 17. ...
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... INTERRUPT register, 2.C502h 2 WIS Local Fault NOT(SONET frame sync) (linked to 2.1.7) Reserved, set undefined if LEGACY = 1. 2. Valid in QT2032 WAN mode only. In QT2022, these alarms are Reserved, RO (including QT2032 in LAN mode). 64 AppliedMicro - Confidential & Proprietary MDIO Status Register Definition (RO) LEGACY=1 16b hex 1.9003.0 1 ...
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DOM receive alarm. rx_flag = {OR of (reg 1.A071.n ‘bit wise AND’ reg 1.9007.n) for n Table 25: rx_flag Alarm Registers Description Receive Optical Power High Alarm Receive Optical Power Low ...
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QT2022/32 - Data Sheet: DS3051 Table 26: Transmit Alarm Registers (TX_ALARM) (Continued) Description LEGACY=0 PMA transmit local Transmit PLL not fault locked (linked to 1.8.11) latched version of NOT(Fiber transmit PLL locked) txlock (reflects value in 1.C001h.0) latched version of ...
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DOM device and mapped to registers 1.A070h.5:4. The function of these bits is not specifically defined in the XENPAK MSA, but they are used in generating the tx_flag signal in ...
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QT2022/32 - Data Sheet: DS3051 WIS_EXT_ALARM WIS_EXT_ALARM is used to indicate that a WAN-related fault has occurred on the receive path. WIS_EXT_ALARM is the bitwise OR of the WIS Extended Alarms Status Register bits in register 2.C502h. WIS_EXT_ALARM can be ...
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Receive Loss-of-Signal Pin (LOSOUTB) LOSOUTB indicates when the input signal applied at RXIN/P is below a threshold which can be adjusted via the resistor connected to the ITH_LOS pin. LOSOUTB=0 indicates that the signal is below the threshold. The ...
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... Low-Speed Output Pins (QT2032 only) The pins described in this section apply to the QT2032 only. These pins are not defined for the QT2022 product. All the low-speed output pins have the same type of open drain driver. An external 10-22 k Ω pullup resistor to 1 expected. The open drain configuration allows these signals to be wire or’ ...
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Each LED driver can be independently programmed to monitor either the transmit path or the receive path, con- trolled by bit 3 of the LED Configuration Registers. LED1 monitors the transmit path by default, while LED2 and LED3 monitor the ...
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... The hysteresis is fixed for a given alarm threshold. The analog LOS detector is always enabled. If the pin is left open (no resistor to ground) the LOS detector will never assert. Please consult AMCCs’ Application Note “Implementing LOS for the QT2022/QT2032” for more information on design practices with the LOS feature. 72 AppliedMicro - Confidential & ...
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MDIO Interface The management data input output (MDIO) interface provides a simple, two wire, serial interface to connect a sta- tion management entity (STA) and a managed PHY for the purpose of controlling the PHY and gathering status from ...
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QT2022/32 - Data Sheet: DS3051 9.4 MDIO Bus Initialization The MDIO bus requires a valid LAN reference clock to be supplied to the EREFCLK input to initialize after powerup or hard reset. The chip will not respond as expected to ...
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Table 32: Management Frame Format Management Frame Fields FRAME PRE ST ADDRESS 1...1 00 WRITE 1...1 00 READ 1...1 00 READ-INC 1...1 00 Revision 5.11 AppliedMicro - Confidential & Proprietary OP PRTAD DEVAD 00 PRTAD[4:0] DA[4:0] 01 PRTAD[4:0] DA[4:0] 11 ...
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QT2022/32 - Data Sheet: DS3051 Figure 23: MDIO Frame Structure Device Management Interface - Address Frame Structure MDC MDIO Write 0 32 “1”s Idle Preamble ST Device Management Interface - Write Frame Structure MDC MDIO Write 0 32 “1”s Idle ...
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Operation Code Field (OP) The Operation Code field describes the major function of the frame. Four frame types are supported, correspond- ing to the frames shown in figure 23 on page 76. The OP Codes for each frame type ...
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... PMA/PMD type control through eeprom • tx_flag and rx_flag for generating LASI ALARM • PMA/PMD Identifier (OUI) See “QAN0026: QT2022C1 & QT2032A1 Implementation and Usage Tips for XFP Applications”, referenced in Table 77, for more information. 78 AppliedMicro - Confidential & Proprietary Revision 5.11 ...
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Two Wire (EEPROM) Interface The EEPROM interface is a standard two-wire interface that can be used as a master to control peripheral devices slave to allow control by other devices. The primary application for this interface ...
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QT2022/32 - Data Sheet: DS3051 Table 34: XENPAK EEPROM Register Map MDIO register EEPROM reg address address 0 0 32775 8007 : 6 6 32781 800D 7 7 32782 800E : 17 11 32792 8018 : 43 2B 32818 8032 ...
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Table 34: XENPAK EEPROM Register Map (Continued) MDIO register EEPROM reg address address : 255 FF 33030 8106 a bits 15:8 of the MDIO registers are reserved (RO) and will return a value of 0 when read. 10.1 EEPROM Data ...
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QT2022/32 - Data Sheet: DS3051 10.1.3 Acknowledge The transmitting device releases the EEPROM_SDA line after transmitting eight data or address bits. During the ninth cycle the receiving device will pull the EEPROM_SDA line low to acknowledge that it received the ...
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Figure 28: EEPROM 256 Byte Read Cycle Timing address byte 00000000 slave address EEPROM address ...
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QT2022/32 - Data Sheet: DS3051 Figure 29: EEPROM 8 Byte Page Write Cycle Timing slave address random access write to word address 0 10.4 EEPROM Single Byte ...
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... Figure 30: QT2022/32 DOM Application Diagram QT2032/ QT2022 The current 256 NVR registers will continue to be read from an external EEPROM with device address 1010000. NVR register mapping and update control conform to the XENPAK MSA. MDIO device number 1 is used for the NVR registers and DOM registers on QT2022/32. ...
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QT2022/32 - Data Sheet: DS3051 10.5.2 rx_flag and tx_flag DOM Alarm Fields rx_flag and tx_flag alarm signals will be generated by the QT2022/32 using information read from MDIO DOM diagnostic alarm registers 1.A070h and 1.A071h and MDIO NVR diagnostic alarm ...
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When the DOM automatic upload mode is selected, the ‘command complete’ or ‘idle’ state will be changed to the ‘command in progress’ state upon the start of a new self initiated upload. This STA read of the ...
Page 88
QT2022/32 - Data Sheet: DS3051 A AMCC-specific DOM write command has been added. The write control is via MDIO vendor specific register 1.C004h. The write can be a full 256 byte write or a single byte write to the address ...
Page 89
Two-byte Addressing of Peripheral I2C Devices To allow a single device on the I2C bus to store the entire DOM and EEPROM memory space, the QT2022/32 can be configured to support 64kB rather than 256 bytes within an I2C ...
Page 90
QT2022/32 - Data Sheet: DS3051 Figure 33: 2-Byte Addressing for EEPROM Read Cycle Timing slave address ...
Page 91
Register Configuration from External EEPROM All MDIO registers can be configured through upload from external EEPROMs. This feature can be used to change the value of any MDIO register from the default without requiring an MDIO command. The new ...
Page 92
... QT2022/32 - Data Sheet: DS3051 Figure 36: EEPROM Register Configuration and DOM Upload Sequence After Reset hardware or software reset QT2032/QT2022 registers reset DOM update rate set to single update NVR update queued, NVR command in progress state set EEPROM_SCL=1, EEPROM_SDA=Z MDIO reset registers cleared Send 9 STOP conditions on I2C ...
Page 93
... MDIO device ID and MDIO register starting address. Address loca- tion 125 (7Dh) stores the MDIO device ID (for the QT2032 devices and 4 are supported; for the QT2022 only devices 1, 3 and 4 are supported). Address 126 (7Eh) stores the upper byte of the register address to be accessed, while address 127 (7Fh) stores the lower byte ...
Page 94
QT2022/32 - Data Sheet: DS3051 10.8.2 Reading and Writing Using the I2C Interface To initiate read or write transactions to an MDIO register, the Device ID and Register Address must be set. Three I2C write commands must be performed to ...
Page 95
Figure 37: MDIO Register Indirect Access Memory Mapping for I2C Access 2-Wire Serial Address 0- 123 124 125 126 127 MDIO Register Data[15:8] for 128 Device ID[7:0] Register Address[15:0] MDIO Register Data[7:0] for 129 Device ID[7:0] Register Address[15:0] MDIO Register ...
Page 96
... The Loopback Data Override bits are set default for all system loopbacks 2. The WIS system loopback feature is available on the QT2032 product only. When in any system (PMA, PCS or XGXS system) loopback mode the QT2022/32 shall accept data from the transmit path and return it on the receive path. During PMA system loopback, the PMA transmit data will default to an all 0’ ...
Page 97
To use this feature, ensure that RxXAUI_SEL = 0. If RxXAUI_SEL = 1 while the analog loopback feature is enabled, the RxXAUI3 output may have additional jitter. Figure 38: Loopback and test pattern generator/checker locations Revision 5.11 AppliedMicro - Confidential ...
Page 98
QT2022/32 - Data Sheet: DS3051 11.2 XAUI Interface Test Features 11.2.1 XAUI PRBS7 Pattern Generator XAUI PRBS, or XAUI BIST, test mode enables the 2 lane. The PRBS pattern is generated using the polynomial 1 The ...
Page 99
Error Checkers For each lane, there is a dedicated 8 bit error counter for checking 8b/10b coding errors on the XAUI input. Each counter works independently. The error counters are located in bits 7:0 of registers 4.C030h - ...
Page 100
... In the QT2032, this counter is available in both LAN and WAN operation controlled by a different bit depending on the mode. The same 16-bit counter register is used in both modes. The control and counter registers are listed in Table 42 on page 101 ...
Page 101
... PMA system loopback. Figure 40: PRBS31 Pattern Checker S0 PRBS31 Pattern Error . Table 42: PRBS31 Generator and Checker Control LAN mode Item (QT2022 and QT2032) PRBS31 Generator Control Register bit 3.42.4 (3.2Ah.4) PRBS31 Checker Control Register bit 3.42.5 (3.2Ah.5) 16-bit Error Counter 3.43 (3.2B) Revision 5.11 AppliedMicro - Confidential & ...
Page 102
... BER test, as this will clear the error counter and give incorrect results. Table 43: BER Test Procedure Step # Step 1 Write 1 to MDIO 3.42.5 in LAN mode (2.7.5 in WAN mode - QT2032 only) This enables the PRBS 2 2 Write desired length of BER test in seconds to 3.C001h.15:0 3 write 1 to 3.C000h.12 ...
Page 103
... Section BIP Error Counter Register 2.60 (2.3Ch). The ‘receive test pattern enable’ bit 2.7.2 does not need to be set enable error checking. 11.6 Ethernet Packet Generator/Checker (QT2032 and QT2022) The QT2022/32 has the ability to generate data packets for test purposes. There is one such generator in the TX path and one in the RX path ...
Page 104
QT2022/32 - Data Sheet: DS3051 11.6.2 Packet Generator Characteristics • The generator can output complete packets with either fixed or incremental data. This is called the packet type feature and is controlled via register 3.C020h.5:4. • When fixed data is ...
Page 105
Activate both generators. Set them to Burst Mode and Fixed Data Type. Do this by writing 16’h0103 to register 3.C020h. 12. Wait sufficiently long to receive all packets within one burst. Calculate the required delay based on packet length, ...
Page 106
... If an asynchronous reference clock is sup- plied and the chip must perform a rate compensation, error codes will be generated. This feature does not work on the QT2032 when operating in WAN mode. 11.8 Test Access Port and Boundary Scan The QT2022/32 has a test-access port (TAP) and a boundary scan (BSCAN) chain compliant with IEEE standards 1149 ...
Page 107
TAP Port Table 44 lists the supported BSCAN instructions while Table 45 lists the unsupported BSCAN instructions.. Table 44: Supported BSCAN Instructions BSCAN Instruction BYPASS EXTEST IDCODE SAMPLE/PRELOAD RUNBIST DEBUGBIST SCAN EXTEST_TRAIN EXTEST_PULSE . Table 45: Unsupported BSCAN Instructions ...
Page 108
QT2022/32 - Data Sheet: DS3051 Table 47: BSCAN Chain Implementation Pins on BSCAN Chain BSCAN Order TDCC 67 TDCC_CLK 66 MDC 65 MDIO 64 MDIO 63 MDIO 62 LED3 61 LED3 60 LED3 59 LED2 58 LED2 57 LED2 56 ...
Page 109
... XAUI. • No incomplete ||R|| or ||K|| ordered sets appear on the XAUI bus as these have a likelihood of being cor- rectly identified as idle columns. Revision 5.11 AppliedMicro - Confidential & Proprietary (QT2032 and QT2022) Query from Device A QT2032/ QT2022 Device B Query from Device B QT2022/32 - Data Sheet: DS3051 ...
Page 110
QT2022/32 - Data Sheet: DS3051 12.2 Query message format In order to identify a remote device, the local device must initiate a series of “queries”. These are specially format- ted PCS-R 66B code blocks which can be detected by and ...
Page 111
Terminate Format The Terminate consists of an all control 66B block with the K28.5 8B/10B code used in payload C must be used in the remaining C 0 Table 50: AppliedMicro Terminate Block Format Input Data Sync bits C ...
Page 112
QT2022/32 - Data Sheet: DS3051 12.5 Transmit State Diagram Figure 43: Extended Link Monitoring Transmit State Diagram query cnt > IDLE State ==> query_cnt = 0, idle_cnt = SENDING State ==> transmit query when ...
Page 113
Receive State Diagram Figure 44: Extended Link Monitoring Receive State Diagram QT Function 1 Enable TD2_1 Function 1 Disable || Function 1 Complete TD0 = IDLE State TD1 = READY TO TX DATA State TD2_1 = FUNCTION#1 IN PROGRESS ...
Page 114
QT2022/32 - Data Sheet: DS3051 To perform a RMDIO read transaction, the user needs to: • Enable the RMDIO feature for transmission in the local PHY by writing Register bit 3.CC08.0. • Enable the RMDIO feature for ...
Page 115
Table 51: RMDIO START Block Format Input Data Sync bits 8’h1e Table 52: RMDIO TERM Block Format Input Data Sync bits C ...
Page 116
QT2022/32 - Data Sheet: DS3051 Transmission of the pseudo-random blocks cannot be enabled unless the ‘AMCC part detected’ bit 3.CC01h.0 is set to 1. When the ‘Extended Link Monitoring RX Enable’ bit 3.CC00h.1 is set default), ...
Page 117
... QT2022/32 MII Register Map The QT2022/32 implements the following register maps defined by the IEEE 802.3 Specification, Clause 45: • 10G PMA/PMD (device 1) • 10G WIS (device 2) - QT2032 only • 10G PCS (device 3) • 10G PHY XGXS (device 4) As well, there are a number of vendor specific registers which are used for additional functionality, testability and observability ...
Page 118
QT2022/32 - Data Sheet: DS3051 13.1 PMA/PMD Internal Control Registers (Device 1) Bit 0 PMA Loop Back Disable PMA Loopback, default 1 = Enable PMA Loopback 1 Reserved Speed Selection operation at ...
Page 119
Bit 0 Reserved Power down capability ability to power down 2 Receive Link Status, RO/ PMA receive link down 1 = PMA locked to the receive signal PMA locked to the receive signal ...
Page 120
... QT2022/32 - Data Sheet: DS3051 Bit 0 Clause 22 registers not present in package PMA/PMD present in package WIS present in package (QT2032 WIS not present in package (QT2022 PCS present in package PHY_XS present in package DTE_XS not present in package 15:6 Reserved, RO Bit 14:0 Reserved vendor specific device not present in package, RO ...
Page 121
... Device present Value of 1 valid for QT2032 only. 2. The field is linked to an MDIO latched high diagnostic alarm register bit. When either register is read both bits will be cleared. The alarm definition depends on Legacy pin input state, as per Table 19 on page 58. Revision 5.11 AppliedMicro - Confidential & ...
Page 122
QT2022/32 - Data Sheet: DS3051 Bit PMD Transmit Disable 1.9 0 PMD Transmit Disable 1 = Transmit disable 0 = Transmit enable (default PMD lane PMD lane PMD ...
Page 123
Bit 0 EEPROM NVR Read/Write Byte Count, RW bit1 bit0 Command reserved 0 1 reserved 1 0 read or write 1 byte 1 1 read or write 256 bytes (default) 2 Command Status, RO/LH bit3 bit2 Command ...
Page 124
QT2022/32 - Data Sheet: DS3051 RX_ALARM Control Bit reg 36864 reg 1.9000h LEGACY=1 0 PHY_XS receive local fault enable enabled, default 1 rx_flag enable 0 = disabled, default 2 PCS receive code violation enable 0 =disabled, default ...
Page 125
Bit 0 LS_ALARM enable, RW 0=disabled, default 1 TX_ALARM enable, RW 0=disabled, default 2 RX_ALARM enable, RW 0=disabled, default 3 LASI INTB enable, RW 0=disabled, default 6:4 Reserved LASI test data enable, RW 15:8 Reserved, RO Revision 5.11 ...
Page 126
... WIS Alarm Interrupt Flag is high if any bit of MDIO Register 2.33 (2.21h) is set and its associated enable bit in MDIO Register 2.C500h is set as well. 3. Register bit type is Reserved, RO for the QT2022 and the QT2032 when LANMODE = 1. 4. WIS Extended Alarm Interrupt Flag is high if any bit of MDIO Register 2.C502h is set and its associated enable bit in MDIO Register 2 ...
Page 127
Bit 0 LS_ALARM, RO/ status change status change) 1 TX_ALARM TX_ALARM condition alarm 2 RX_ALARM RX_ALARM condition alarm 3 Interrupt from LASI_INTB pin, ...
Page 128
QT2022/32 - Data Sheet: DS3051 Bit 1.A000-1.A06Fh 0 LSB, bit 0 Laser Output Power Low Alarm Laser Output Power High Alarm Laser Bias Current Low Alarm Laser Bias Current High Alarm, ...
Page 129
Bit 6 Reserved Reserved DOM Command Byte Count Control 256 bytes (default byte 9 Reserved Reserved Reserved DOM Write Command Status (RO, LH) bit3 ...
Page 130
QT2022/32 - Data Sheet: DS3051 Bit 0 txlock , RO 1=Fiber transmit PLL in lock 1 sync_err , RO/LH 1=recovered clock rate error 2 TXPLLOUT Output Frequency Select This pin reverses the sense of the XFP input for determining TXPLLOUT ...
Page 131
Bit 6 RXPLLOUT Enable, RW 0=RXPLLOUT disabled except in line timing mode (default) 1=RXPLLOUT enabled 7 LAN Reference Input Select 0 = use EREFCLK input (default use TXPLLOUT input (disables TXPLLOUT output driver) In conjunction with MDIO 1.C001h.3, ...
Page 132
QT2022/32 - Data Sheet: DS3051 PMA/PMD Vendor PMA/PMD Vendor Specific Specific Bit Register 1.C002h 0 I2C/DOM single byte EEPROM NVR 256 byte write read/write address, RW cycle burst size size bit1 bit0 Reserved, ...
Page 133
Bit 4:0 I2C Address Extension in 2 Byte Addressing Mode (RW) 15:5 Reserved, RO Bit 0 EEPROM_SCL tristate not tristate, default 1 = tristate 1 Bypass EEPROM Powerup Wait (RW Normal EEPROM Operation (default) 1 ...
Page 134
QT2022/32 - Data Sheet: DS3051 PMA Vendor Specific AMCC Test Patterns Control Bit 0 Enable TX Fibre for AMCC Test Pattern 0 = Disable, Default 1 = Enable 1 Select AMCC Test Pattern on TX Fibre 0 = Static, Default ...
Page 135
... Register value ignored for QT2022, or QT2032 in LAN mode. Memory BIST Mode Register 0 Bit 1.C100h 0 Done 1 Control Select 2:5 Algorithm Select 6 Pause 7 Error 8 Debug Mode 12:9 Pattern 14:13 Port 15 Upper Mode Register Memory BIST Memory BIST Debug Bit Register 0 1.C103h 7:0 Data [15:0], RO ...
Page 136
QT2022/32 - Data Sheet: DS3051 Bit 2:0 BIST Select (RW BIST 0, Memory 0 (default BIST 1, Memory BIST 2, Memory BIST 2, Memory BIST 3, Memory ...
Page 137
... Product code Reserved, RO Fourth Character Product code Reserved, RO Third Character Product code Metal Code, RO Second Character Product code Version Code, RO First Character QT2022/32 - Data Sheet: DS3051 PMA Vendor Specific AMCC Revision Code 1.D001h QT2032 QT2022 Reserved Reserved Metal Code Version Code 137 ...
Page 138
QT2022/32 - Data Sheet: DS3051 PMA Vendor Specific Bit AMCC Input Pads Status 1.D002h 0 RxXAUI_SEL TxXAUI_SEL TXON TXOUT_SEL RXIN_SEL TXFAULT RXLOSB_I LASI_INTB ...
Page 139
PMA Vendor Specific Bit AMCC Output Pads Status 1.D004h 0 LASI TXENABLE LOSOUTB LTIMEOK , RO 15:4 Reserved Pin is not defined for QT2022. Bit 0 LED1/GPIO1 Configuration Control ...
Page 140
QT2022/32 - Data Sheet: DS3051 Bit 0 LED2/GPIO2 Configuration Control Reserved Link Status Only Link Activity Only Link ...
Page 141
... WIS Registers (Device 2) (QT2032 only) The Device 2 registers are defined for the QT2032 only. For the QT2022, writes to these registers are ignored. Reads from these registers will return all 0’s. Bit WIS Control 1 Reg 2.0 0 Reserved, RO 6:1 Speed selection (RO): always 5’ ...
Page 142
QT2022/32 - Data Sheet: DS3051 Bit 0 WIS is capable of operating at 10 Gb/s, RO always 1 15:1 Reserved, RO Bit Device in package Register 2.5 0 Clause 22 register present (RO) always 0 1 PMD/PMA present (RO) always ...
Page 143
... This register bit can be used to enable/disable the WIS in the QT2032. Refer to Section 7, “WAN Interface Sublayer (WIS) Descrip- tion (QT2032 Only),” on page 36 for details. This bit is “sticky”; it maintains its value after a soft reset (a reset from an MDIO com- mand). The default value is restored after a hard reset (applied to RESETN input pin). ...
Page 144
QT2022/32 - Data Sheet: DS3051 Bit 10G WIS Status 3 Register (2.33) 2.0021h 0 LOP-P (RO/LH): Loss of Pointer 1 AIS-P (RO/LH): Alarm Indication signal 2 PLM-P (RO/LH): Loss of Label Mismatch 3 LCD-P (RO/LH): Path loss of cell delineation ...
Page 145
Reg WIS J1 Tx Registers (2.39-2.46) 2.27h - 2.2Eh 2. (RW): 7:0 Transmitted Path Trace Octet 2. (RW): 15:8 Transmitted Path Trace Octet 2. (RW): 7:0 Transmitted Path ...
Page 146
QT2022/32 - Data Sheet: DS3051 Reg WIS J1 Rx Registers (2.47-2.54) 2.2Fh - 2.36h 2. (RO): 7:0 Received Path Trace Octet 2. (RO): 15:8 Received Path Trace Octet 2.48 J1 ...
Page 147
Reg WIS Line BIP-8 Errors Registers (2.57-2.58) 2.39h-2.3Ah 2.57 WIS Line BIP-8 Error 0 (RO) (Most significant word of the WIS Line BIP-8 Error count) 2.58 WIS Line BIP-8 Error 1 (RO) (Least significant word of the WIS Line BIP-8 ...
Page 148
QT2022/32 - Data Sheet: DS3051 Reg WIS J0 Tx Registers (2.64-2.71) 2.40h - 2.47h 2. (RW): 7:0 Transmitted Section Trace Octet 2. (RW): 15:8 Transmitted Section Trace Octet 2.65 J0 ...
Page 149
Reg WIS J0 Rx Registers (2.72-2.79) 2.0048h - 2.004Fh 2. (RO): 7:0 Received Section Trace Octet 2. (RO): 15:8 Received Section Trace Octet 2. (RO): 7:0 Received Section ...
Page 150
QT2022/32 - Data Sheet: DS3051 Bit WIS Frame Pointer - Vendor Specific Register 2.C000h 0 Received Invalid Pointer (RO/LH) Triggered when positive stuff events are not separated more frames. 1 Received Invalid Pointer (RO/LH) Triggered under any ...
Page 151
Bit WIS Vendor Specific Control - Vendor Specific Register 2.C001h 0 WIS scrambler bypass (RW Bypass not asserted (default Bypass asserted 1 WIS descrambler bypass (RW Bypass not asserted (default Bypass asserted ...
Page 152
QT2022/32 - Data Sheet: DS3051 Bit WIS Serial Interface Control - Vendor Specific Register 2.C010h 2:0 WIS Serial Interface Mode of Operation on Transmit Path (RW) 001 = Use serial data for all STS-1 Transport Overhead 100 = Use serial ...
Page 153
Reg WIS J1 Rx Extended Registers 2.C100h - 2.C117h (Continued) 2.C10Bh J1 Rx Byte #40 (MSB Byte #39 (LSB) - (RO) 2.C10Ch J1 Rx Byte #42 (MSB Byte #41 (LSB) - (RO) 2.C10Dh J1 Rx Byte ...
Page 154
QT2022/32 - Data Sheet: DS3051 Reg WIS J1 Tx Extended Registers 2.C200h - 2.C217h (Continued) 2.C20Eh J1 Tx Byte #46 (MSB Byte #45 (LSB) - (RW) 2.C20Fh J1 Tx Byte #48 (MSB Byte #47 (LSB) - ...
Page 155
Bit WIS K2 Rx Byte - Vendor Specific Register 2.C303h 7:0 Validated K2 Byte Value (RO) 15:8 Received K2 Byte Value (RO) Bit WIS S1 Tx Byte - Vendor Specific Register 2.C304h 7:0 S1 Byte Value to Transmit (RW) default ...
Page 156
QT2022/32 - Data Sheet: DS3051 Bit WIS SD Coding Violations Count - Vendor Specific Register 2.C403h 15:0 Coding Violation Count over the last timing window (RO) Bit WIS SF Timing Window - Vendor Specific Register 2.C410h 15:0 Programmable timing window ...
Page 157
Bit WIS Alarms Interrupt Control 0 LOP-P Enable (RW Disabled (default Enabled 1 AIS-P Enable (RW Disabled (default Enabled 2 PLM-P Enable (RW Disabled (default Enabled 3 LCD-P ...
Page 158
QT2022/32 - Data Sheet: DS3051 Bit WIS Extended Alarms Interrupt Control 0 K1 Validated Byte Enable (RW Disabled (default Enabled 1 K2 Validated Byte Enable (RW Disabled (default Enabled 2 Received Inconsistent ...
Page 159
Bit WIS Extended Alarms Status - Vendor Specific Register 2.C502h 0 K1 Validated Byte Flag (RO/LH Validated Byte Flag (RO/LH) 2 Received Inconsistent K1 Bytes Flag (RO/LH) 3 Received Inconsistent K2 Bytes Flag (RO/LH Validated Byte ...
Page 160
QT2022/32 - Data Sheet: DS3051 Bit WIS OH Insert Byte 1 Control - Vendor Specific Register 2.C601h 1:0 STS-1 Column Number (RW) Valid Values: from 5:2 STS-1 Row Number (RW) Valid Values: from 13:6 ...
Page 161
Bit WIS OH Insert Byte 1 Value - Vendor Specific Register 2.C604h 7:0 Overwrite Byte Value (RW) 15:8 Reserved (RO) Bit WIS OH Insert Byte 2 Value - Vendor Specific Register 2.C605h 7:0 Overwrite Byte Value (RW) 15:8 Reserved (RO) ...
Page 162
QT2022/32 - Data Sheet: DS3051 Bit WIS OH Extract Byte 1 Control - Vendor Specific Register 2.C611h 1:0 STS-1 Column Number (RW) Valid Values: from Path Overhead Bytes) 5:2 STS-1 Row Column Number (RW) Valid ...
Page 163
Bit WIS OH Extracted Byte 2 Value - Vendor Specific Register 2.C615h 7:0 Extracted Byte Value (RO) 15:8 Reserved (RO) Bit WIS OH Extracted Byte 3 Value - Vendor Specific Register 2.C616h 7:0 Extracted Byte Value (RO) 15:8 Reserved (RO) ...
Page 164
QT2022/32 - Data Sheet: DS3051 13.3 PCS Registers (Device 3) PCS Control 1 Bit Register 3.0 0 Reserved Reserved Speed Selection operation at 10 Gb/s 3 Speed Selection operation at ...
Page 165
... Reserved, RO Revision 5.11 AppliedMicro - Confidential & Proprietary PCS Devices in Package Register 3.5 0, Clause 22 registers not present in package PMA/PMD present in package WIS present in package (QT2032 WIS not present in package (QT2022 PCS present in package PHY_XS present in package DTE_XS not present in package, RO Reserved, RO Reserved, RO ...
Page 166
QT2022/32 - Data Sheet: DS3051 PCS Control 2 Bit Register 3.7 0 bit1 bit0 0 0 Select 10GBASE-R PCS 1 0 Select 10GBASE-W PCS R/W, writes ignored 1 2 Reserved Reserved Reserved Reserved, RO ...
Page 167
Base-R PCS Jitter Test Pattern Seed A Bit Registers Registers 3.34 3. bit 0, RW bit 16 ...
Page 168
QT2022/32 - Data Sheet: DS3051 10GBASE-R PCS Jitter Bit Test Pattern Control Register 3.42 (3.2Ah) 0 pattern select, RW 1=zeros data pattern 0=LF data pattern 1 test pattern select square wave test pattern 0= pseudo random test ...
Page 169
Bit 0 PCS: LOP-P Mask Enable 1= defect does not propagate to PCS 0= defect propagates to PCS (default) 1 PCS: AIS-P Mask Enable 1= defect does not propagate to PCS 0= defect propagates to PCS (default) 2 PCS: PLM-P ...
Page 170
QT2022/32 - Data Sheet: DS3051 PCS Vendor Specific Bit Packet Generator Control 3.C020 Packet Generator Enable , Disable, Default 1 = Enable Packet Generator Enable , Disable, Default ...
Page 171
PCS Vendor Specific Packet Generator Bit Burst Size 3.C024h 15:0 Burst Size, RW Default = 16’d256 PCS Vendor Specific Packet Checker Bit Control 3.C030h Packet Checker Enable , Disable, Default 1 = Enable 1 ...
Page 172
QT2022/32 - Data Sheet: DS3051 PCS Vendor Specific RX Packet Checker Bit Error Counter 3.C034h 15:0 Rx Error Detected Counter, RO cleared upon read non-rollover Extended Line Bit Monitoring Control 3.CC00h 0 Extended Link Monitoring TX Enable ...
Page 173
Rx Pseudo-Random Block Counter Bit 3.CC05h 15:0 Received Pseudo-Random Block Non-rollover latched on read cleared on read of 3.CC06h RMDIO Bit Control 3.CC08h 0 PHY RMDIO feature TX enable disabled, default 1 = enabled 1 PHY RMDIO ...
Page 174
QT2022/32 - Data Sheet: DS3051 RMDIO Status Bit 3.CC0Bh 0 RMDIO Read Request Sent, RO/LH 1 RMDIO Write Request Sent, RO/LH 2 RMDIO Read Response Received, RO/LH 3 RMDIO Write Response Received, RO/LH 4 Reserved Reserved ...
Page 175
PHY_XS Registers (Device 4) PHY_XS Control 1 Bit 4.0 0 Reserved Reserved Speed Selection operation at 10 Gb/s 3 Speed Selection operation at 10 Gb/s 4 Speed Selection, RO ...
Page 176
... Bit Register 4 PCS is capable of operat- 0, Clause 22 registers not present in ing at 10 Gb/s, RO package Reserved PMA/PMD present in package Reserved WIS present in package (QT2032 WIS not present in package (QT2022 Reserved PCS present in package Reserved PHY_XS present in package Reserved DTE_XS not present in package Reserved, RO ...
Page 177
PHY XGXS Bit Lane Status Register 4.24 (4.18h) 0 Lane 0 sync, RO 1=lane is in sync 1 Lane 1 sync, RO 1=lane is in sync 2 Lane 2 sync, RO 1=lane is in sync 3 Lane 3 sync, ...
Page 178
QT2022/32 - Data Sheet: DS3051 PHY_XS Vendor Bit Specific Register 4.C000h 0 Transmit XGXS reset, RW 0=reset 1= not reset, default Note: not self clearing 1 Receive XGXS reset, RW 0=reset 1= not reset, default Note: not self clearing 2 ...
Page 179
PHY_XS Vendor Bit Specific Register 4.C000h 6 xtxlock<2> = lane 2 lock, RO 1=lane 2 in lock 7 xtxock<3> = lane 3 lock, RO 1=lane 3 in lock 8 1 CJPAT Generator Enable , disable, default 1 ...
Page 180
QT2022/32 - Data Sheet: DS3051 Bit 5:0 Reserved XGXS Rx rate adjust underflow 1 = underflow linked to 1.9003h.6 7 XGXS Rx rate adjust overflow 1 = overflow linked to 1.9003h.6 8 XGXS Tx rate adjust underflow 1 ...
Page 181
PHY_XS Vendor Specific Bit Register 4.C005h 0 Reserved Reserved Reserved Reserved, RO 11:4 Reserved XAUI Lane 0 Clock Phase Error, RO/ Clock Phase Error 13 XAUI Lane 1 Clock Phase ...
Page 182
QT2022/32 - Data Sheet: DS3051 PHY_XS Vendor Specific AMCC Test Patterns Bit 0 Enable XAUI Lane 0 for AMCC Test Pattern 0 = Disable, Default 1 = Enable 1 Enable XAUI Lane 1 for AMCC Test Pattern 0 = Disable, ...
Page 183
Bit 0 Force XAUI Driver VCO 0 = Disable, Default 1 = Force VCO 1 Select XAUI Driver VCO Forced Frequency 0 = MIN Freq, Default 1 = MAX Freq 2 Force XAUI CDR VCO 0 = Disable, Default 1 ...
Page 184
QT2022/32 - Data Sheet: DS3051 Bit 6 Monitor XAUI Lane 2 CDR Control Voltage 0 = Disable, Default 1 = Monitor Signal 7 Monitor XAUI Lane 3 CDR Control Voltage 0 = Disable, Default 1 = Monitor Signal 8 Override ...
Page 185
Bit TX Ratecomp Override Enable Register 4.C040h 0 Reserved, RO 15:1 Reserved, RO Bit TX Ratecomp Control1 Register 4.C041h 7:0 TX Rate Control1 Value (RW) 15:8 Reserved, RO Bit TX Ratecomp Control3 Register 4.C043h 7:0 TX Rate Control3 Value (RW) ...
Page 186
QT2022/32 - Data Sheet: DS3051 Bit RX Ratecomp Control1 Register 4.C051h 7:0 RX Rate Control1 Value (RW) 15:8 Reserved, RO Bit RX Ratecomp Control3 Register 4.C053h 7:0 RX Rate Control3 Threshold Value (RW) 15:8 Reserved, RO Bit 7:0 RX Rate ...
Page 187
Table 55: Operating Conditions Parameter Description Ta Ambient temperature 1.2V supply voltages P Power consumption in XFP mode (XFP = 1) P Power consumption in XENPAK mode (XFP=0) Power consumption in Low Power Mode (TXON = 0) I ...
Page 188
QT2022/32 - Data Sheet: DS3051 Table 56: 190B LBGA Package Constants Parameter Description θ Junction-to-Case Thermal Resistance JC θ Junction-to-Ball Thermal Resistance JB θ Junction-to-Ambient Thermal Resistance JA θ Note that was calculated using boundary conditions defined in JESD51-8. Note ...
Page 189
Table 59: JTAG AC Parameters Parameter Description fmax TCK operating frequency Tsu TDI, TMS input setup time requirement Thd TDI, TMS input hold time requirement Tdel TDO output propagation delay 1. Timing is measured from the point where signals cross ...
Page 190
QT2022/32 - Data Sheet: DS3051 Table 61: MDIO AC Parameters Parameter Description Tdelay delay from MDC rising edge to MDIO data output edge See Note. Fmax MDC clock rate MDC high and low times OPERATION UNDER LOW CAPACITIVE LOAD (1.2V ...
Page 191
Table 63: EEPROM_SDA & EEPROM_SCL 3.3V Bidirectional Pad DC Parameters Parameter Description Cload external load capacitance Rpu external pullup resistance to Vpu Table 64: EEPROM Interface AC Parameters Parameter Description f EEPROM_SCL clock frequency SCL t EEPROM_SCL low time low ...
Page 192
... Applies when TXPLLOUT configured as an input. 2. QT2032 only. 3. The device will work properly in WAN mode with +-100ppm frequency tolerance. However, SONET com- patible applications require a +-20ppm tolerance. 192 AppliedMicro - Confidential & ...
Page 193
Table 67: XAUI Input Interface Parameter Description BAUD Rate See Note 1. BAUD Rate tolerance Differential input amplitude and Input Compliance Mask Differential input impedance |S11D| Differential return loss (referenced to Ω 100 ) Common mode return loss Ω (referenced ...
Page 194
QT2022/32 - Data Sheet: DS3051 Figure 46: XAUI Driver Far End Template Differential Amplitude mVpp Table 68: XAUI Driver Characteristics Parameter Description BAUD Rate See Note 3. Differential Eye Height (opening) See Note 1. Transition times Total Output jitter, TJ ...
Page 195
Table 68: XAUI Driver Characteristics Parameter Description Note 3: Baud rate is specified relative to the reference clock frequency in Table 66 on page 191 Note 4: Measured using a low-frequency square-wave pattern to allow for settling of the waveform ...
Page 196
QT2022/32 - Data Sheet: DS3051 Table 69: Serial Receiver Specifications (Continued) Parameter Description SCC11 Common-mode input return loss SCD11 Differential to common-mode conversion JTOL_XFP Jitter amplitude tolerance JTOL_ nonXFP Eye Mask in XFP mode Tl CDR Lock Time at Start-up ...
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... The LOS detector output is seen at pin LOSOUTB. The LOS assert and deassert thresholds trigger off of the input signal amplitude. Please consult AMCCs’ Application Note “Implementing LOS for the QT2022/QT2032” for more information on design practices with the LOS feature. ...
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... LOSOUTB High Low Table 71: Serial Transmitter Specifications Parameter Description f LAN Mode TXOUT nominal bit rat WAN Mode nominal bit rate (QT2032 only) Zse single-ended output impedance Zd differential output impedance Zm Single-ended impedance mismatch Differential Output Amplitude Tr, Tf Output Rise and Fall Times ...
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... Table 71: Serial Transmitter Specifications (Continued) Parameter Description TJ LAN Mode Total jitter WAN Mode Total Output Jitter (TJ) (QT2032 only) See Note 3. Eye Mask See Note 3. Note 1: Return Loss given by equation SDD22(dB 16.6Log10(f/7.5), with f in GHz Note 2: Measured using a low-frequency square-wave pattern to allow for settling of the waveform resulting in an accurate topline and baseline reference ...
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QT2022/32 - Data Sheet: DS3051 Table 72: TXPLLOUT Reference Clock Output Specifications (XFP=1) Parameter Description single-ended load impedance differential load impedance differential swing (p-p) duty cycle rise/fall time frequency See Note 1. See Table 8 on page 35. BAUD rate ...