DSPIC33EP256MU806-E/MR Microchip Technology, DSPIC33EP256MU806-E/MR Datasheet - Page 555

• Manufacturer Part Number: DSPIC33EP256MU806-E/MR
• Description: 64 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP256MU806-E/MR

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 12K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Revision C (May 2011)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
These global changes were implemented:
• All instances of V
• References to remappable pins have been
• The minimum V
The major changes are referenced by their respective
section in
TABLE A-2:
 2009-2011 Microchip Technology Inc.
High-Performance, 16-bit Digital
Signal Controllers and
Microcontrollers
Section 2.0 “Guidelines for
Getting Started with 16-bit Digital
Signal Controllers and
Microcontrollers”
Section 3.0 “CPU”
Section 4.0 “Memory
Organization”
Section 5.0 “Flash Program
Memory”
Section 6.0 “Resets”
Section 11.0 “I/O Ports”
Section 17.0 “Quadrature
Encoder Interface (QEI) Module
(dsPIC33EPXXXMU806/810/814
Devices Only)”
updated to clarify output-only pins (RPn) versus
input/output pins (RPIn).
3.0V to adhere to the current BOR specification.
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
Table
Section Name
A-2.
DD
MAJOR SECTION UPDATES
DDCORE
value was changed from 2.7V to
have been removed.
Removed the shading for D+/RG2 and D-/RG3 pin designations in all pin
diagrams, as these pins are not 5V tolerant.
References to remappable pins have been updated to clarify input/output pins
(RPn) and input-only pins (RPIn).
Add information on the V
Requirements”.
Updated the title of Section 2.3 to Section 2.3 “CPU Logic Filter Capacitor
Connection (V
Added Note 2 to the Programmer’s Model Register Descriptions
(see Table 3-1).
Added the CANCKS bit (CxCTRL1<11>) to the ECAN1 and ECAN 2 Register
Maps (see Table 4-26 and Table 4-29).
Added the SBOREN bit (RCON<13>) to the System Control Register Map (see
Table 4-43).
Added Note 1 to the PORTG Register maps (see Table 4-60 and Table 4-61).
Updated the Page Description for DSRPAG = 0x1FF and DSRPAG = 0x200 in
Table 4-66.
Updated the second paragraph of Section 4.2.9 “EDS Arbitration and Bus
Master Priority”.
Updated the last note box in Section 4.2.10 “Software Stack”.
Updated the equation formatting in Section 5.3 “Programming Operations”.
Added the Non-Volatile Memory Upper Address (NVMADRU) and Non-Volatile
Memory Address (NVMADR) registers (see Register 5-2 and Register 5-3).
Added Security Reset to the Reset System Block Diagram (see Figure 6-1).
Added the SBOREN bit (RCON<13>) and Notes 3 and 4 to the Reset Control
register (see Register 6-1).
References to remappable pins have been updated to clarify input/output pins
(RPn) and input-only pins (RPIn).
Added the new column, Input/Output, to Input Pin Selection for Selectable Input
Sources (see Table 11-2).
Updated the definition for the INTHLD<31:0> bits (see Register 17-19 and
Register 17-20).
Preliminary
CAP
)” and modified the first paragraph.
USB
Update Description
pin in Section 2.1 “Basic Connection
DS70616E-page 555