DSPIC33EP256MU806-E/MR Microchip Technology, DSPIC33EP256MU806-E/MR Datasheet - Page 364

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DSPIC33EP256MU806-E/MR

Manufacturer Part Number
DSPIC33EP256MU806-E/MR
Description
64 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33EPr
Datasheet

Specifications of DSPIC33EP256MU806-E/MR

Core Processor
dsPIC
Core Size
16-Bit
Speed
60 MIPs
Connectivity
CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
51
Program Memory Size
256KB (85.5K x 24)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
12K x 16
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
REGISTER 22-9:
REGISTER 22-10: UxCNFG1: USB CONFIGURATION REGISTER 1
DS70616E-page 364
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7-0
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
UTEYE
R/W-0
R/W-0
U-0
U-0
When the UTRIS (UxCNFG2<0>) bit is set, the OE signal is active regardless of the setting of UOEMON.
Unimplemented: Read as ‘0’
CNT<7:0>: Start of Frame Count bits
Value represents 10 + (packet size of n bytes); for example:
0100 1010 = 64-byte packet
0010 1010 = 32-byte packet
0001 0010 = 8-byte packet
Unimplemented: Read as ‘0’
UTEYE: USB Eye Pattern Test Enable bit
1 = Eye pattern test enabled
0 = Eye pattern test disabled
UOEMON: USB OE Monitor Enable bit
1 = OE signal active; it indicates intervals during which the D+/D- lines are driving
0 = OE signal inactive
Unimplemented: Read as ‘0’
USBSIDL: USB OTG Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
Unimplemented: Read as ‘0’
UOEMON
R/W-0
R/W-0
U-0
U-0
UxSOF: USB OTG START-OF-TOKEN THRESHOLD REGISTER
(HOST MODE ONLY)
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
R/W-0
U-0
U-0
U-0
(1)
USBSIDL
R/W-0
R/W-0
U-0
U-0
Preliminary
CNT<7:0>
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
R/W-0
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
 2009-2011 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
R/W-0
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
bit 8
bit 0
bit 8
bit 0

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