DSPIC33EP256MU806-E/MR Microchip Technology, DSPIC33EP256MU806-E/MR Datasheet - Page 299

• Manufacturer Part Number: DSPIC33EP256MU806-E/MR
• Description: 64 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP256MU806-E/MR

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 12K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 17-2:
 2009-2011 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-11
bit 10-9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
HOMPOL
QCAPEN
R/W-0
R/W-0
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
QCAPEN: Position Counter Input Capture Enable bit
1 = Positive edge detect of Home input triggers position capture function
0 = HOMEx input event (positive edge) does not trigger a capture event
FLTREN: QEAx/QEBx/INDXx/HOMEx Digital Filter Enable bit
1 = Input Pin Digital filter is enabled
0 = Input Pin Digital filter is disabled (bypassed)
QFDIV<2:0>: QEAx/QEBx/INDXx/HOMEx Digital Input Filter Clock Divide Select bits
111 = 1:256 clock divide
110 = 1:64 clock divide
101 = 1:32 clock divide
100 = 1:16 clock divide
011 = 1:8 clock divide
010 = 1:4 clock divide
001 = 1:2 clock divide
000 = 1:1 clock divide
OUTFNC<1:0>: QEI Module Output Function Mode Select bits
11 = The CTNCMPx pin goes high when QEIxLEC  POSxCNT  QEIxGEC
10 = The CTNCMPx pin goes high when POSxCNT  QEIxLEC
01 = The CTNCMPx pin goes high when POSxCNT  QEIxGEC
00 = Output is disabled
SWPAB: Swap QEA and QEB Inputs bit
1 = QEAx and QEBx are swapped prior to quadrature decoder logic
0 = QEAx and QEBx are not swapped
HOMPOL: HOMEx Input Polarity Select bit
1 = Input is inverted
0 = Input is not inverted
IDXPOL: HOMEx Input Polarity Select bit
1 = Input is inverted
0 = Input is not inverted
QEBPOL: QEBx Input Polarity Select bit
1 = Input is inverted
0 = Input is not inverted
QEAPOL: QEAx Input Polarity Select bit
1 = Input is inverted
0 = Input is not inverted
HOME: Status of HOMEx Input Pin After Polarity Control
1 = Pin is at logic ‘1’
0 = Pin is at logic ‘0’
FLTREN
IDXPOL
R/W-0
R/W-0
QEIxIOC: QEI I/O CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
QEBPOL
R/W-0
R/W-0
QFDIV<2:0>
QEAPOL
R/W-0
R/W-0
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
HOME
R/W-0
R-x
INDEX
R/W-0
R-x
OUTFNC<1:0>
x = Bit is unknown
R/W-0
QEB
R-x
DS70616E-page 299
SWPAB
R/W-0
QEA
R-x
bit 8
bit 0