DSPIC33EP256MU806-E/MR Microchip Technology, DSPIC33EP256MU806-E/MR Datasheet - Page 263

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DSPIC33EP256MU806-E/MR

Manufacturer Part Number
DSPIC33EP256MU806-E/MR
Description
64 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
dsPIC™ 33EPr
Datasheet

Specifications of DSPIC33EP256MU806-E/MR

Core Processor
dsPIC
Core Size
16-Bit
Speed
60 MIPs
Connectivity
CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
51
Program Memory Size
256KB (85.5K x 24)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
12K x 16
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-VFQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
REGISTER 15-1:
 2009-2011 Microchip Technology Inc.
bit 2-0
Note 1:
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
OCxR and OCxRS are double-buffered in PWM mode only.
OCM<2:0>: Output Compare Mode Select bits
111 = Center-Aligned PWM mode: Output set high when OCxTMR = OCxR and set low when
110 = Edge-Aligned PWM mode: Output set high when OCxTMR = 0 and set low when
101 = Double Compare Continuous Pulse mode: Initialize OCx pin low, toggle OCx state continuously
100 = Double Compare Single-Shot mode: Initialize OCx pin low, toggle OCx state on matches of
011 = Single Compare mode: Compare events with OCxR, continuously toggle OCx pin
010 = Single Compare Single-Shot mode: Initialize OCx pin high, compare event with OCxR, forces
001 = Single Compare Single-Shot mode: Initialize OCx pin low, compare event with OCxR, forces OCx
000 = Output compare channel is disabled
OCxTMR = OCxRS
OCxTMR = OCxR
on alternate matches of OCxR and OCxRS
OCxR and OCxRS for one cycle
OCx pin low
pin high
OCxCON1: OUTPUT COMPAREx CONTROL REGISTER 1 (CONTINUED)
(1)
(1)
Preliminary
DS70616E-page 263

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