DSPIC33EP256MU806-E/MR Microchip Technology, DSPIC33EP256MU806-E/MR Datasheet - Page 117

• Manufacturer Part Number: DSPIC33EP256MU806-E/MR
• Description: 64 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP256MU806-E/MR

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 12K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.2.9
EDS accesses from bus masters in the system are
arbitrated.
The arbiter for data memory (including EDS) arbitrates
between the CPU, the DMA, the USB module, and the
ICD module. In the event of coincidental access to a
bus by the bus masters, the arbiter determines which
bus master access has the highest priority. The other
bus masters are suspended and processed after the
access of the bus by the bus master with the highest
priority.
By default, the CPU is bus master 0 (M0) with the
highest priority, and the ICD is bus master 4 (M4) with
the lowest priority. The remaining bus masters (USB
and DMA Controllers) are allocated to M2 and M3,
TABLE 4-67:
Note 1:
FIGURE 4-8:
 2009-2011 Microchip Technology Inc.
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
DPSRAM
M0 (highest)
M4 (lowest)
Priority
M1
M2
M3
All other values of MSTRPR<15:0> are Reserved.
EDS ARBITRATION AND BUS
MASTER PRIORITY
MSTRPR<15:0>
EDS BUS ARBITER PRIORITY
ARBITER ARCHITECTURE
Reserved
0x0000
DMA
CPU
USB
ICD
DMA
Preliminary
Reserved
MSTRPR<15:0> Bit Setting
0x0008
DMA
USB
CPU
ICD
USB
M0
respectively (M1 is reserved and cannot be used). The
user application may raise or lower the priority of the
masters to be above that of the CPU by setting the
appropriate bits in the EDS Bus Master Priority Control
(MSTRPR) register. All bus masters with raised
priorities will maintain the same priority relationship
relative to each other (i.e., M1 being highest and M3
being lowest with M2 in between). Also, all the bus
masters with priorities below that of the CPU maintain
the same priority relationship relative to each other.
The priority schemes for bus masters with different
MSTRPR values are tabulated in
This bus master priority control allows the user
application to manipulate the real-time response of the
system, either statically during initialization, or
dynamically in response to real-time events.
M1
EDS Arbiter
SRAM
M2
ICD
Reserved
0x0020
DMA
CPU
USB
ICD
M3
(1)
M4
CPU
Table
DS70616E-page 117
Reserved
0x0028
4-67.
Reserved
DMA
USB
CPU
ICD