DSPIC33EP256MU806-E/MR Microchip Technology, DSPIC33EP256MU806-E/MR Datasheet - Page 164

• Manufacturer Part Number: DSPIC33EP256MU806-E/MR
• Description: 64 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP256MU806-E/MR

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 12K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
9.1
The
PIC24EPXXXGU810/814 family of devices provide
seven system clock options:
• Fast RC (FRC) Oscillator
• FRC Oscillator with Phase-Locked Loop (PLL)
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
• Secondary (LP) Oscillator
• Low-Power RC (LPRC) Oscillator
• FRC Oscillator with postscaler
FIGURE 9-2:
EQUATION 9-2:
EQUATION 9-3:
DS70616E-page 164
Where,
N1 = PLLPRE + 2
N2 = 2 x (PLLPOST + 1)
M = PLLDIV + 2
F
VCO
F
IN
CPU Clocking System
dsPIC33EPXXXMU806/810/814
=
F
IN
PLLPRE<4:0>
0.8 MHz < F

÷ N1


------ -
N1
M
PLL BLOCK DIAGRAM
F
F


OSC
VCO
F
=
OSC
F
REF
CALCULATION
CALCULATION
IN
=

< 8.0 MHz
F


F
------------------------------------ -


IN
REF
PLLPRE
PLLDIV



-------------------- -
N1 N2
PFD
M

+
+
2
2






and
=
Preliminary
F
IN

PLLDIV<8:0>


VCO
÷ M
--------------------------------------------------------------------------------------- -

PLLPRE
120 MH
Instruction execution speed or device operating
frequency, F
EQUATION 9-1:
Figure 9-2
Equation 9-2
frequency (F
Equation 9-3
frequency (F
F

Z
+
VCO
PLLDIV
< F
2

is a block diagram of the PLL module.
VCO

CY
IN
IN
2 PLLPOST

) and output frequency (F
) and VCO frequency (F
provides the relation between input
provides the relation between input
, is given by
< 340 MH
+
PLLPOST<2:0>
2
 2009-2011 Microchip Technology Inc.

÷ N2
F
CY
DEVICE OPERATING
FREQUENCY
Z
= Fosc/2
+
Equation
1



F
F
OSC
OSC
< 120 MHz
9-1.
VCO
OSC
).
).