DSPIC33EP256MU806-E/MR Microchip Technology, DSPIC33EP256MU806-E/MR Datasheet - Page 129

• Manufacturer Part Number: DSPIC33EP256MU806-E/MR
• Description: 64 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP256MU806-E/MR

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 12K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-VFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.0
The Reset module combines all reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
• MCLR: Master Clear Pin Reset
• SWR: RESET Instruction
• WDTO: Watchdog Timer Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Condition Device Reset
FIGURE 6-1:
 2009-2011 Microchip Technology Inc.
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
Note 1: This data sheet summarizes the features
dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
2: Some registers and associated bits
RESETS
of the dsPIC33EPXXXMU806/810/814
and PIC24EPXXXGU810/814 families of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Reset”
(DS70602) of the “dsPIC33E/PIC24E
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
MCLR
V
DD
Uninitialized W Register
Configuration Mismatch
RESET SYSTEM BLOCK DIAGRAM
Regulator
RESET Instruction
Internal
Sleep or Idle
Security Reset
Illegal Opcode
Module
WDT
Trap Conflict
V
Detect
DD
Glitch Filter
Rise
Preliminary
BOR
POR
in
A simplified block diagram of the Reset module is
shown in
Any active source of Reset will make the SYSRST sig-
nal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state and some are unaffected.
All types of device Reset sets a corresponding status
bit in the RCON register to indicate the type of Reset
(see
A POR clears all the bits, except for the POR and BOR
bits (RCON<1:0>), that are set. The user application
can set or clear any bit at any time during code
execution. The RCON bits only serve as status bits.
Setting a particular Reset status bit in software does
not cause a device Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note:
Note:
Register
Figure
Refer to the specific peripheral section or
Section 4.0 “Memory Organization”
this manual for register Reset states.
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
6-1).
6-1.
SYSRST
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