ADAU1445YSVZ-3A-RL Analog Devices Inc, ADAU1445YSVZ-3A-RL Datasheet - Page 30

• Manufacturer Part Number: ADAU1445YSVZ-3A-RL
• Description: 175MHZ SigmaDSP,2x8 SRCs
• Manufacturer: Analog Devices Inc
• Series: SigmaDSP®r
• Type: Audio Processorr

Specifications of ADAU1445YSVZ-3A-RL

• Applications: Automotive Audio
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Format: Fixed Point
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADAU1445/ADAU1446
Table 17. Configurations for Standard Audio Data Formats
Format
I
Left-Justified
Right-Justified
TDM with Clock
TDM with Pulse
2
S
(Figure 22)
(Figure 23)
(Figure 24)
(Figure 25)
(Figure 26)
SDATA_IN0
SDATA_IN1
SDATA_IN2
SDATA_IN3
SDATA_IN4
SDATA_IN5
SDATA_IN6
SDATA_IN7
SDATA_IN8
CLOCK DOMAINS
DEDICATED
0
0 TO 2
INPUT
2
(×3)
1
2
LRCLK Polarity
Frame begins on
falling edge
Frame begins on
rising edge
Frame begins on
rising edge
Frame begins on
falling edge
Frame begins on
rising edge
2
2
SERIAL
SERIAL
MODES
PORTS
INPUT
3
INPUT
18:2
(×9)
(×9)
4
5
6
7
8
LRCLK Type
Clock
Clock
Clock
Clock
Pulse
4:2
CLOCK DOMAIN
2
SELECTOR
Figure 21. Overview of Serial Data Input/Output Ports
INPUT
4:2
2
BCLK Polarity
Data changes on falling edge
Data changes on falling edge
Data changes on falling edge
Data changes on falling edge
Data changes on falling edge
4:2
INPUT/OUTPUT
Rev. A | Page 30 of 92
ASSIGNABLE
DSP CORE
DOMAINS
2
3 TO 8
FARM
(×6)
AND
4:2
2
CLOCK DOMAIN
4:2
SELECTOR
OUTPUT
2
4:2
2
MULTIPLEXERS
MSB Position
Delayed from LRCLKx edge by 1 BCLK
Aligned with LRCLKx edge
Delayed from LRCLKx edge by 8, 12, or 16 BCLKs
Delayed from start of frame clock by 1 BCLK
Delayed from start of frame clock by 1 BCLK
CLOCK PAD
3
4
5
OUTPUT
OUTPUT
SERIAL
MODES
SERIAL
PORTS
6
(×9)
18:2
(×9)
7
CLOCK DOMAINS
8
DEDICATED
9 TO 11
OUTPUT
9
2
(×3)
SDATA_OUT0
SDATA_OUT1
SDATA_OUT2
SDATA_OUT3
SDATA_OUT4
SDATA_OUT5
SDATA_OUT6
SDATA_OUT7
SDATA_OUT8
10 11
2
2