ADAU1445YSVZ-3A-RL Analog Devices Inc, ADAU1445YSVZ-3A-RL Datasheet - Page 21

• Manufacturer Part Number: ADAU1445YSVZ-3A-RL
• Description: 175MHZ SigmaDSP,2x8 SRCs
• Manufacturer: Analog Devices Inc
• Series: SigmaDSP®r
• Type: Audio Processorr

Specifications of ADAU1445YSVZ-3A-RL

• Applications: Automotive Audio
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Format: Fixed Point
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PLL Loop Filter
The PLL loop filter should be connected to the PLL_FILT pin. This
filter, shown in Figure 11, includes three passive components—
two capacitors and a resistor. The values of these components
do not need to be exact; the tolerance can be up to 10% for the
resistor and up to 20% for each capacitor. The 3.3 V signal shown
in the schematic can be connected to the PVDD supply of the chip.
Using the ADAU1445/ADAU1446 as Clock Masters
To output a master clock from the ADAU1445/ADAU1446 to
other chips in the system, the CLKOUT pin is used. To set the
frequency of this clock signal, the CLKMODEx pins must be set
(see Table 8).
Table 8. CLKOUT Modes
CLKOUT Signal
Disabled
Buffered Oscillator
256 × f
512 × f
S,NORMAL
S,NORMAL
1.8nF
Figure 11. PLL Loop Filter
PLL_FILT
CLKMODE1
0
0
1
1
PVDD
ADAU1445/
ADAU1446
1.5kΩ
33nF
CLKMODE0
0
1
0
1
Rev. A | Page 21 of 92
Master Clock and PLL Modes and Settings
DSP Core Rate Select Register (Address 0xE220)
The core’s start pulse initiates the operation of the core and
determines the sample rate of signals processed inside the core.
This pulse can originate from one of three internally generated
f
signals (an LRCLK signal associated with a serial input port),
one of the 12 serial output f
with a serial output port), or LRCLK recovered from the S/PDIF
receiver input.
Setting the value of the DSP core rate select register sets the speed
of the DSP core (see Table 10). By default, the signals processed
in the core are at the normal DSP core rate; therefore, the core
clock is 3584 × f
core at the dual rate, the start pulse should be set to the internally
generated dual rate, and the core clock is 1792 × f
system processing signals in the core at the quad rate, the start
pulse should be set to the internally generated quad rate, and
the core clock is 896 × f
Master Clock Enable Switch Register (Address 0xE280)
For power-saving purposes, various parts of the chip can be
switched on and off. Setting the appropriate bit to 0 disables the
corresponding subsystem, and setting the bit to 1 enables the
subsystem. This is the first register that should be set after the
device is powered on and completes its initialization. Failure to
set this register may compromise future register writes.
Table 9. Bit Descriptions of Register 0xE280
Bit Position
[15:9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
1
2
S
0 = disable, 1 = enable.
See the Flexible Audio Routing Matrix—Input Side section for more
information.
signals (f
S,NORMAL
Description
Reserved
Enable MCLK to auxiliary ADCs
Enable MCLK to S/PDIF transmitter
Enable MCLK to S/PDIF receiver
Enable MCLK to DSP core
Enable MCLK to Stereo ASRC[7:4]
Enable MCLK to Stereo ASRC[3:0]
Enable MCLK to serial outputs
Enable MCLK to serial inputs
Enable MCLK to flexible audio routing
matrix (FARM)
S, NORMAL
, f
S,DUAL
. For a system processing signals in the
S,QUAD
, or f
S
signals (an LRCLK signal associated
1
.
S,QUAD
ADAU1445/ADAU1446
), one of the 12 serial input f
2
2
S,DUAL
. For a
Default
0
0
0
0
0
0
0
0
0
S