ADAU1445 Analog Devices, ADAU1445 Datasheet
ADAU1445
Specifications of ADAU1445
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ADAU1445 Summary of contents
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... Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. SigmaDSP Digital Audio Processor with Flexible Audio Routing Matrix ADAU1442/ADAU1445/ADAU1446 and SPI control interfaces Standalone operation ...
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... ADAU1442/ADAU1445/ADAU1446 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Specifications..................................................................................... 5 Digital Timing Specifications ..................................................... 8 Absolute Maximum Ratings.......................................................... 11 Thermal Resistance .................................................................... 11 ESD Caution................................................................................ 11 Pin Configuration and Function Descriptions........................... 12 Theory of Operation ...................................................................... 17 System Block Diagram............................................................... 17 Overview...................................................................................... 18 Initialization ................................................................................ 20 Master Clock and PLL ............................................................... 21 Voltage Regulator ....................................................................... 25 SRC Group Delay ...
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... Added Multipurpose Pin Value Registers (Address 0x129A to Address 0x12A5) Section and Table 66; Renumbered Sequentially..................................................................................68 Change to Table 84..........................................................................82 Changes to Ordering Guide...................................................................91 ADAU1442/ADAU1445/ADAU1446 4/09—Rev Rev. A Added ADAU1446 ............................................................. Universal Added LQFP ....................................................................... Universal Added Minimum Digital Current (DVDD) of ADAU1446, Maximum Digital Current (DVDD) of ADAU1446, and AVDD, DVDD, PVDD During Operation of ADAU1446 Parameters, Table 1 ...
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... ASRCs and are packaged in TQFP packages, whereas the ADAU1446 contains no ASRCs and is packaged in an LQFP. The ADAU1442 can handle nine clock domains, the ADAU1445 can handle three clock domains, and the ADAU1446 can handle one clock domain. The ADAU1442/ADAU1445/ADAU1446 can be controlled in ...
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... Rev Page ADAU1442/ADAU1445/ADAU1446 = 172.032 MHz, CORE Unit Test Conditions/Comments AVDD = 3.3 V ± 10%. Bits V LSB LSB LSB kΩ kHz 4:1 multiplexed input, each channel at f /3584. For CORE f = 172.032 MHz, each CORE channel is sampled at 48 kHz. ...
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... ADAU1442/ADAU1445/ADAU1446 Parameter I/O Sample Rate Ratio THD + N CRYSTAL OSCILLATOR Transconductance 2 REGULATOR DVDD Voltage 1 To calculate the group delay, refer to the SRC Group Delay section. 2 Regulator specifications are calculated using an NJT4030P transistor from On Semiconductor in the circuit. AVDD = 3.3 V ± 10%, DVDD = 1.8 V ± 10%, PVDD = 3.3 V, IOVDD = 3.3 V ± 10%, T core clock f = 172 ...
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... I/O Current (IOVDD) Maximum Digital Current (DVDD) ADAU1442 ADAU1445 ADAU1446 Power Dissipation AVDD, DVDD, PVDD During Operation of ADAU1442 AVDD, DVDD, PVDD During Operation of ADAU1445 AVDD, DVDD, PVDD During Operation of ADAU1446 Reset, All Supplies ASYNCHRONOUS SAMPLE RATE 2 CONVERTERS Dynamic Range I/O Sample Rate I/O Sample Rate Ratio ...
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... ADAU1442/ADAU1445/ADAU1446 DIGITAL TIMING SPECIFICATIONS T = −40°C to +105°C, DVDD = 1.8 V, IOVDD = 3 Table 4. 1 Parameter Min MASTER CLOCK f 2.822 MP t 40. CLKOUT Jitter CORE CLOCK f CORE SERIAL PORT f BCLK t 40.69 BCLK t 30 BIL t 30 BIH t 20 LIS t 20 LIH t 10 SIS t 10 ...
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... CLOCKS (16-BIT DATA) MSB – SIS MSB t SIH t SIS MSB t SIH Figure 2. Serial Input Port Timing MSB – SODS t SODM MSB t SODS t SODM MSB Figure 3. Serial Output Port Timing Rev Page ADAU1442/ADAU1445/ADAU1446 t LIH t SIS LSB t SIH LSB t TS ...
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... ADAU1442/ADAU1445/ADAU1446 t CLS t CLATCH CCPH CCLK CDATA t CDS COUT SDA SCL t MCLK RESET t CCPL t CDH Figure 4. SPI Port Timing SCH t t SCLR SCLH SCS SCLL SCLF 2 Figure Port Timing MP t RLPW Figure 6. Master Clock and Reset Timing Rev Page ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ADAU1442/ADAU1445/ADAU1446 THERMAL RESISTANCE θ is specified for the worst-case conditions, that is, a device JA soldered in a circuit board for surface-mount packages ...
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... ADAU1442/ADAU1445/ADAU1446 TOP VIEW (Not to Scale) Figure 7. Pin Configuration Description Digital Ground. The AGND, DGND, and PGND pins should be tied directly together in a common ground plane. DGND pins should be decoupled to a DVDD pin with a 100 nF capacitor. Input and Output Supply. The voltage on this pin sets the highest input voltage that should be present on the digital input pins ...
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... Self-Boot Select. Allows the ADAU1442/ADAU1445/ADAU1446 to be controlled by the control port or to perform a self-boot. Setting this pin high (that is initiates a self-boot operation when the ADAU1442/ADAU1445/ADAU1446 are brought out of a reset. This pin can be tied directly to a voltage source or ground or pulled up/down with a resistor. ...
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... Crystal Oscillator Input. This pin provides the master clock for the ADAU1442/ADAU1445/ADAU1446. If the ADAU1442/ADAU1445/ADAU1446 generate the master clock in the system, this pin should be connected to the crystal oscillator circuit. If the ADAU1442/ADAU1445/ADAU1446 are slaves to an external master clock, this pin should be connected to the master clock signal generated by another IC ...
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... Input/Output Clock Domain 5 is set master or slave. When not used, this pin can be left disconnected. Serial Data Port 1 Output. When not used, this pin can be left disconnected. Serial Data Port 4 Input. When not used, this pin can be left disconnected. Rev Page ADAU1442/ADAU1445/ADAU1446 ...
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... ADAU1442/ADAU1445/ADAU1446 Pin No. Mnemonic Type 1 96 BCLK4 D_IO 97 LRCLK4 D_IO 98 SDATA_OUT0 D_OUT 99 SDATA_IN3 D_IN 1 PWR = power/ground, A_IN = analog input, D_IN = digital input, A_OUT = analog output, D_OUT = digital output, D_IO = digital input/output. Description Bit Clock, Input/Output Clock Domain 4. This pin is bidirectional, with the direction depending on whether the Input/Output Clock Domain 4 is set master or slave ...
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... DELAY MEMORY CHANNELS OF ASYNCHRONOUS SAMPLE RATE CONVERTERS SERIAL CLOCK DOMAINS (×12 DGND AVDD AGND IOVDD Figure 8. System Block Diagram Rev Page ADAU1442/ADAU1445/ADAU1446 PLL[2:0] PLL_FILT XTALI, XTALO CLOCK PLL OSCILLATOR 2 CLKMODE[1:0] CLOCK OUTPUT CLKOUT S/PDIF SPDIFO TRANSMITTER ...
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... Handshaking is included for ease of memory uploads and downloads. The ADAU1442/ ADAU1445/ADAU1446 can be configured for either SPI or I control. Program RAM, parameter RAM, and register contents can be saved in an external EEPROM, from which the ADAU1442/ ADAU1445/ADAU1446 can self-boot on startup ...
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... The ADAU1442/ADAU1445/ADAU1446 are fabricated on a single monolithic integrated circuit for operation over the −40°C to +105°C temperature range. The ADAU1442 and ADAU1445 are housed in a 100-lead TQFP package, with an exposed pad to assist in heat dissipation, and the ADAU1446, due to its lower power consumption, is housed in a 100-lead LQFP package ...
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... New values should not be written via the control port until the initialization is complete. Table 8 shows some typical times to boot the ADAU1442/ ADAU1445/ADAU1446 into the operational state necessary for an 2 application, assuming that a 400 kHz I C clock MHz SPI clock is used and a full program, parameter set, and all registers (9 kB) are loaded ...
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... S,DUAL If the ADAU1442/ADAU1445/ADAU1446 cores are set to receive quad-rate signals (by reducing the number of program steps per sample by a factor of 4 using the DSP core rate select register), then the master clock frequency must be 16 × × ...
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... ADAU1442/ADAU1445/ADAU1446 Table 9. PLL Modes Input to MCLK DSP Core Rate 1 (XTALI Pin) Normal 64 × f S,NORMAL 128 × f S,NORMAL 256 × f S,NORMAL 384 × f S,NORMAL 512 × f S,NORMAL Dual 32 × f S,DUAL 64 × f S,DUAL 128 × f S,DUAL 192 × f S,DUAL 256 × f S,DUAL Quad 16 × ...
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... PLL_FILT Figure 11. PLL Loop Filter Using the ADAU1442/ADAU1445/ADAU1446 as Clock Masters To output a master clock from the ADAU1442/ADAU1445/ ADAU1446 to other chips in the system, the CLKOUT pin is used. To set the frequency of this clock signal, the CLKMODEx pins must be set (see Table 10). Table 10. CLKOUT Modes ...
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... ADAU1442/ADAU1445/ADAU1446 Table 12. Bit Descriptions of Register 0xE220 Bit Position Description [15:5] Reserved [4:0] Start pulse select 00000 = internally generated normal rate (f 00001 = internally generated dual rate (f 00010 = internally generated quad rate (f 00011 = f from serial input Stereo Pair 0 S 00100 = f from serial input Stereo Pair 1 ...
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... V to 1.8 V. The maximum digital current draw of the ADAU1442 and ADAU1445, which use ASRCs, is 310 mA. The equation to determine the minimum power dissipation specifications of the transistor is as follows: (3.3 V − ...
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... Logic Level 0 corresponds to a write operation. Address Bit 5 and Address Bit 6 are set by tying the ADDRx pins of the ADAU1442/ ADAU1445/ADAU1446 to Logic Level 0 or Logic Level 1. Both SDA and SCL should have pull-up resistors on the lines connected to them (a standard value is 2.0 kΩ, but this can be changed depending on the capacitive load on the line) ...
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... This increment happens automatically, unless a stop condition is encountered after a single-word write. The registers and RAMs in the ADAU1445/ ADAU1446 range in width from one to five bytes; therefore, the auto-increment feature knows the mapping between subaddresses and the word length of the destination register (or memory lo- cation) ...
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... R DATA-WORD 1, BYTE 1 2 Figure 18. Burst Mode I C Read Sequence Rev Page ACK BY ADAU1442/ADAU1445/ADAU1446 FRAME 2 SUBADDRESS BYTE 1 ADR R/W SEL ADAU1442/ADAU1445/ADAU1446 FRAME 4 CHIP ADDRESS BYTE ACK BY STOP BY MASTER MASTER FRAME 6 READ DATA BYTE 2 DATA DATA AS AS ... AS BYTE 2 BYTE N ... AS ...
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... The CCLK signal latches CDATA on a low-to-high transition. COUT data is shifted out of the ADAU1442/ ADAU1445/ADAU1446 on the falling edge of CCLK and should be clocked into a receiving device, such as a microcontroller, on the next CCLK falling edge (rising edge is possible met) ...
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... ADAU1442/ADAU1445/ADAU1446 2 acting as masters on the I C bus on startup, which occurs when the SELFBOOT pin is set high. The ADAU1442/ADAU1445/ ADAU1446 cannot self-boot in SPI mode. The maximum necessary EEPROM size is 40,960 bytes kB. This much memory is only needed if the program RAM (4096 × 6 bytes) and parameter RAM (4096 × 4 bytes) are each completely full ...
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... SERIAL DATA INPUT/OUTPUT The flexible serial data input and output ports of the ADAU1442/ ADAU1445/ADAU1446 can be set to accept or transmit data 2-channel (usually I S format), packed TDM4, or standard 4-, 8-, or 16-channel TDM stream. Data is processed in twos complement, MSB-first format. The left-channel data field always precedes the right-channel data field in 2-channel streams ...
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... ADAU1442/ADAU1445/ADAU1446 Table 19. Configurations for Standard Audio Data Formats Format LRCLK Polarity Frame begins on (Figure 22) falling edge Left-Justified Frame begins on (Figure 23) rising edge Right-Justified Frame begins on (Figure 24) rising edge TDM with Clock Frame begins on (Figure 25) falling edge TDM with Pulse Frame begins on ...
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... LRCLK BCLK DATA MSB MSB – 1 MSB – 2 Figure 25. TDM Mode SLOT 1 SLOT 2 SLOT 3 SLOT 4 Figure 26. TDM Mode with Pulse Frame Clock Rev Page ADAU1442/ADAU1445/ADAU1446 RIGHT CHANNEL MSB LSB RIGHT CHANNEL LSB RIGHT CHANNEL MSB SLOT 6 SLOT 7 SLOT 8 MSB TDM CH ...
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... The ADAU1442 contains eight 2-channel ASRCs and the ADAU1445 contains two 8-channel ASRCs, whereas the ADAU1446 contains no ASRCs. However, all clock domain pins are available on every device system with no sample rate ...
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... ASSIGNABLE INPUT/OUTPUT CLOCK DOMAINS (×6) Figure 28. Clock Pad Multiplexer Rev Page ADAU1442/ADAU1445/ADAU1446 1 Clock Domain Reserved Clock Domain 8 Clock Domain 7 Clock Domain 6 Clock Domain 5 Clock Domain 4 Clock Domain 3 TO SERIAL OUTPUT PORTS CLOCK PAD ...
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... ADAU1442/ADAU1445/ADAU1446 Packed TDM4 Mode A special TDM mode is available that allows four channels to be fit into a space of 64 bit clock cycles. This mode is called packed TDM4 mode, or MOST™ mode. MOST (Media Oriented Systems Transport networking standard intended for interconnecting multimedia components in automobiles and other vehicles. Many ICs intended to interface with a MOST bus use a packed TDM4 data format ...
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... In slave mode, the clock domain selector (that is, the 18:2 multiplexer) allows each serial input port to clock from any available clock domain. In master mode, the ADAU1442/ADAU1445/ADAU1446 clock domain selector is bypassed, and the assignments described in Table 24 are used. The maximum number of audio channels that can be input to SigmaDSP is 24 ...
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... ADAU1442/ADAU1445/ADAU1446 SDATA_IN0 SDATA_IN1 SDATA_IN2 SDATA_IN3 SDATA_IN4 SDATA_IN5 SDATA_IN6 SDATA_IN7 SDATA_IN8 DEDICATED INPUT CLOCK DOMAINS (×3) SERIAL INPUT PORTS (×9) CLOCK DOMAIN 18:2 SELECTOR (× 4:2 4:2 4:2 4:2 4 ASSIGNABLE INPUT/OUTPUT CLOCK DOMAINS (×6) Figure 30. Input Serial Port Clock Multiplexing Rev ...
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... S,NORMAL S,DUAL S,QUAD Rev Page ADAU1442/ADAU1445/ADAU1446 Read/Write Hex Name Word Length E000 Serial Input Port 0 modes 16 bits (2 bytes) E001 Serial Input Port 1 modes 16 bits (2 bytes) E002 Serial Input Port 2 modes 16 bits (2 bytes) ...
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... ADAU1442/ADAU1445/ADAU1446 Bit Position Description [7:6] Word length bits bits bits 11 = flexible TDM mode [5:3] MSB position 2 000 = I S (delayed by 1) 001 = left justified (delayed by 0) 010 = delayed by 8 011 = delayed by 12 100 = delayed by 16 [2:0] TDM type 000 = TDM2 (stereo) 001 = TDM4 ...
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... Mode section. If the word length bits (Bits[7:6]) are set to 11 for flexible TDM mode, then TDM type bits (Bits[2:0]) must also be set for flexible TDM mode (that is, set to 010). In master mode, the ADAU1442/ADAU1445/ADAU1446 can generate either an LRCLK clock signal (50% duty cycle LRCLK synchronization pulse at the specified frequency (f ...
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... ADAU1442/ADAU1445/ADAU1446 selector (that is, the 18:2 multiplexer) allows each serial output port to clock from any available clock domain. In master mode, the clock domain selector is bypassed, and the assignments described in Table 28 are used. Table 28. Output Clock Domain Assignments in Master Mode Data Pin Clock Pins ...
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... Serial Output Port 6 modes 57415 E047 Serial Output Port 7 modes 57416 E048 Serial Output Port 8 modes 57417 E049 High speed slave interface mode ADAU1442/ADAU1445/ADAU1446 Read/Write Word Length 16 bits (2 bytes) 16 bits (2 bytes) 16 bits (2 bytes) 16 bits (2 bytes) 16 bits (2 bytes) 16 bits (2 bytes) 16 bits (2 bytes) 16 bits (2 bytes) ...
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... ADAU1442/ADAU1445/ADAU1446 Table 30. Bit Descriptions of Serial Output Port Modes Registers Bit Position Description 15 Clock output enable 0 = LRCLK and BCLK output pins disabled 1 = LRCLK and BCLK output pins enabled 14 Frame sync type 0 = LRCLK 50/50 duty cycle clock signal (square wave LRCLK synchronization pulse (narrow pulse) ...
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... LRCLKx BCLKx SDATA_OUTx LRCLK POLARITY LRCLKx LRCLKx ADAU1442/ADAU1445/ADAU1446 LRCLKx signal. Standard I polarity. Word Length Bits (Bits[7:6]) These bits set the word length of the input data at 16, 20 bits. The output stream always has space for 24 bits of data, but if the word length is set lower, the extra bits are set as 0s. The fourth setting is flexible TDM ...
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... Routing Matrix Block Diagram Figure 36 shows an overview of audio routing in the ADAU1442/ ADAU1445/ADAU1446 and details the interaction among the S/PDIF I/O, serial I/O, ASRCs, and DSP via the routing matrix. To reduce the complexity of the system, audio signals are routed in pairs. Therefore, in Figure 36, each solid line represents a stereo pair of audio signals ...
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... Routing Matrix Functionality Serial Input Ports The far left side of Figure 36 represents the audio input pins to the ADAU1442/ADAU1445/ADAU1446, namely SDATA_IN0 to SDATA_IN8 and SPDIFI. The serial audio data signals can be represented in any standard mode, including time division multiplexing (TDM) modes, as detailed in the Serial Data Input/Output section ...
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... ASRC (Stereo ASRC 6). Stereo ASRC Input Pair 7 (composed of Channel 14 and Channel 15) corre- sponds to the eighth ASRC (Stereo ASRC 7). In the case of the ADAU1445, there are two 8-channel ASRCs. Therefore, Stereo ASRC Input Pairs[3:0] (composed of Channel 0 to Channel 7) correspond to the first ASRC (Stereo ASRC[3:0]) and must be synchronous to each other ...
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... ASRC pairs. This allows the ASRCs to be placed both before and after the DSP. Figure 43 and Figure 44 show examples of how the ASRCs can be used both before and after the DSP. ASYNCHRONOUS Figure 42. Synchronous and Asynchronous Zones of the ADAU1442 and ADAU1445 ADAU1442/ADAU1445/ADAU1446 FROM DSP FROM ...
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... ADAU1442/ADAU1445/ADAU1446 Sample Rate Conversion Before the DSP If asynchronous input signals are present in the system, they must be routed through the ASRC before being processed by the DSP. This is made possible by routing the asynchronous signals through the input side of the routing matrix to the ASRC inputs. This is illustrated in Figure 43. ...
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... If an output channel is left empty (that is, no data is routed to it from the ASRCs or DSP still assigned to a serial output port. OUTPUT CHANNELS (24 CH 10, 11 12, 13 14, 15 16, 17 18, 19 20, 21 22, 23 Rev Page ADAU1442/ADAU1445/ADAU1446 2 S mode, and ...
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... ADAU1442/ADAU1445/ADAU1446 OUTPUT CHANNELS (24 CH 10, 11 12, 13 14, 15 16, 17 18, 19 20, 21 22, 23 FLEXIBLE AUDIO ROUTING MATRIX MODES AND SETTINGS Table 32. Addresses of Flexible Audio Routing Matrix Modes Registers Address Decimal Hex Name 57472 E080 ASRC input select, Pair 0 (Channel 0, Channel 1) ...
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... DSP core. In the case of the ADAU1442, each input to the stereo ASRCs can receive a separate data input. In the case of the ADAU1445, each input to the stereo ASRCs can receive a separate data input; however, all inputs to Stereo Table 33. Bit Descriptions of ASRC Input Select Pairs[7:0] Registers ...
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... ADAU1442/ADAU1445/ADAU1446 ASRC Input Data Selector Bits (Bits[5:0]) As shown in Figure 49, the gray box representing the input side of the flexible audio routing matrix can be thought multiplexer. Any input to the box can make a one-to-one SDATA_IN0 SDATA_IN1 SDATA_IN2 SDATA_IN3 SDATA_IN4 SDATA_IN5 SDATA_IN6 SDATA_IN7 SDATA_IN8 connection to any output from the box ...
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... In the case of the ADAU1442, each output from the stereo ASRCs can have a separate data output. In the case of the ADAU1445, each output from the stereo ASRCs can have a separate data output; however, all outputs from Stereo ASRC[3:0] must be synchronous to each other, and ...
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... ADAU1442/ADAU1445/ADAU1446 Serial Output Select Pairs[11:0] Registers (Address 0xE090 to Address 0xE09B) Table 35. Bit Descriptions of Serial Output Select Pairs[11:0] Registers Bit Position Description [15:6] Reserved [5:0] Serial output data selector 010000 = DSP Output Pair 0 (Channel 0, Channel 1) 010001 = DSP Output Pair 1 (Channel 2, Channel 3) 010010 = DSP Output Pair 2 (Channel 4, Channel 5) ...
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... Figure 50. Serial Output Select Pair Rev Page ADAU1442/ADAU1445/ADAU1446 SDATA_OUT0 SDATA_OUT1 SDATA_OUT2 SDATA_OUT3 SDATA_OUT4 SDATA_OUT5 SDATA_OUT6 SDATA_OUT7 SDATA_OUT8 ...
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... ADAU1442/ADAU1445/ADAU1446 ASYNCHRONOUS SAMPLE RATE CONVERTERS The integrated sample rate converters of the ADAU1442/ ADAU1445 processors can be configured in various ways to facilitate asynchronous connectivity to other components in the audio system. The sample rate converters operate completely independent of the serial ports and DSP core, connecting via the flexible audio routing matrix ...
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... ASRC will not cause its lock bit to change from 0 back the case of the ADAU1446, setting these registers does not affect system operation in any way. ADAU1442/ADAU1445/ADAU1446 Stereo ASRC[7:4] Mute Ramp Disable Register (Address 0xE143) Table 40. Bit Descriptions of Register 0xE143 ...
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... These include hardware decibel conversion and audio- specific ROM constants. Signal Processing The ADAU1442/ADAU1445/ADAU1446 are designed to provide all signal processing functions commonly used in stereo or multichannel playback systems. The signal processing flow is designed using SigmaStudio software from Analog Devices. This software allows graphical entry and real-time control of all signal processing functions ...
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... A is the number of bits to the left of the decimal point and B is the number of bits to the right of the decimal point. The ADAU1442/ADAU1445/ADAU1446 use the same numeric format for both the parameter and data values. The format is as shown in the Numerical Format: 5.23 section. ...
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... ADAU1442/ADAU1445/ADAU1446 RELIABILITY FEATURES The ADAU1442/ADAU1445/ADAU1446 contain several subsystems designed to increase the reliability of the system in which they are used. When these functions are used in conjunction with an external host controller device, the DSP can recover from serious errors, such as memory corruption or a program counter crash. ...
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... Bit Position Description [15:1] Reserved 0 Watchdog error sticky (read only) ADAU1442/ADAU1445/ADAU1446 Function 1-bit enable register for watchdog timer 16 MSBs of the watchdog maximum count value 16 LSBs of the watchdog maximum count value This single-bit watchdog error flag goes high when an error occurs. It can optionally be sent pin, as described in the Multipurpose Pin Control Registers (Address 0xE204 to Address 0xE20F) section ...
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... ADAU1442/ADAU1445/ADAU1446 RAMS The ADAU1442/ADAU1445/ADAU1446 have 4k words of program RAM, 4k words of parameter RAM, and 8k words of data RAM. Program RAM Table 48. Register Details of Program RAM Address Name Decimal Hex 8192 2000 Program RAM The program RAM contains the 43-bit operation codes that are executed by the core important to note that although the length of the RAM is 4096, only 3584 instructions can be executed in the span of a single frame for normal rate signals ...
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... This ensures that any user data is unaltered at the output and is reintegrated into the audio stream. In the ADAU1442/ADAU1445/ADAU1446, clock recovery is entirely digital result, the ADAU1442/ADAU1445/ ADAU1446 have better protection against clock jitter. The ADAU1442/ADAU1445/ADAU1446 S/PDIF ports are designed to meet the following AES and EBU specifications: a jitter of 0 ...
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... The full channel status information contained in the stream is 24 bytes wide for each channel (that is, 48 bytes in total). The ADAU1442/ADAU1445/ADAU1446 make the first five bytes of the left channel available through 2 I C/SPI ...
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... In general, a loss-of-lock event is much shorter than an ASRC mute or unmute ramp. Rev Page ADAU1442/ADAU1445/ADAU1446 n they are configured so that the auxiliary 10). The hot enable bit is set to 0 automatically in the event P ses lock. For more information utputs— ...
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... ADAU1442/ADAU1445/ADAU1446 2 Enable S/PDIF Output Register (Address 0 Table 64. Bit Descriptions of Register 0xE241 Bit Position Description [15:3] Reserved 2 Output mode TDM 1 Group 2 enable 0 = Group 2 off 1 = Group Group 1 enable 0 = Group 1 off 1 = Group 1 on The S/PDIF receiver can be set to send the stereo audio stream ...
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... MULTIPURPOSE PINS The ADAU1442/ADAU1445/ADAU1446 each incl 12 multipurpo pins that can used either as digital gen purpos e inputs/o utputs (GP IOs inputs to the 4-chan el au xiliary ADC. E ach of the 12 m ultipur pose pins is controlled by a 4-b mode. P ins can be conf igured as d igital inputs, digital outputs, or hen ...
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... ADAU1442/ADAU1445/ADAU1446 AUXILIARY ADC The ADAU1442/ADAU1445/ADAU1446 include a 10-bit auxiliary ADC that can be used for control input signals. There one ADC with four multiplexed inputs. The ADC samples at rate of f /896 (192 kHz when based on a 172.032 MHz core CORE clock), which results in an effective sampling rate of f (48 kHz when based on a 172 ...
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... INTERFACING WITH OTHER DEVICES When interfacing the ADAU1442/ADAU1445/ADAU1446 to oth each pin. DRIVE STRENGTH MODES AND SETTINGS Bit Clock Pad Strength Register (Address 0xE247) This register controls the pad drive strength of all bit clock pins for most applications. The 6 mA setting should be used only Table 71 ...
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... ADAU1442/ADAU1445/ADAU1446 Frame Clock Pad Strength Register (Address 0xE248 This register controls the pad drive strength of all frame clock pins configured in master mode. The default 2 mA setting should be adequate for most applications. The 6 mA setting should be used only when the integrity of the signal is compromised. ...
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... MP3 0 = low strength (2 mA high strength (6 mA) 2 MP2 0 = low strength (2 mA high strength (6 mA) 1 MP1 0 = low strength (2 mA high strength (6 mA) 0 MP0 0 = low strength (2 mA high strength (6 mA) ADAU1442/ADAU1445/ADAU1446 49) ster Rev Page uate Default ...
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... ADAU1442/ADAU1445/ADAU1446 Serial Data Output Pad Strength Register (Address 0xE24A This register controls the pad drive strength of all serial data output pins. The default 2 mA setting should be adequate for most applications. The 6 mA setting should be used only when the integrity of the signal is compromised. ...
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... ADDR0 0 = low strength (2 mA high strength (6 mA) 2 SDA/COUT 0 = low strength (2 mA high strength (6 mA) 1 SPDIFO 0 = low strength (2 mA high strength (6 mA) 0 CLKOUT 0 = low strength (2 mA high strength (6 mA) ADAU1442/ADAU1445/ADAU1446 Rev Page grity of the signal is compromised. Default ...
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... ADAU1442/ADAU1445/ADAU1446 FLEXIBLE TDM MODES The ADAU1442/ADAU1445/ADAU1446 are able to operate in a flexible TDM mode, which allows them to interface to a wide variety of digital audio devices. SERIAL INP UT FLEXIBL E TDM INTE AND SETTINGS Th e flexible TDM mode is av ailable for the SDATA_IN0 and S DATA_IN1 serial input por ts ...
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... Position of the first byte on the TDM stream 000000 = TDM Slot 0 000001 = TDM Slot 1 … 111110 = TDM Slot 62 111111 = TDM Slot 63 ADAU1442/ADAU1445/ADAU1446 odes Reg isters Read/Write Word Length 16 bits (2 bytes) 16 bits (2 bytes) 16 bits (2 bytes) 16 bits (2 bytes) 16 bits (2 bytes) ...
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... ADAU1442/ADAU1445/ADAU1446 SERIAL OUTPUT FLEXIBLE TDM INTERFACE MODES AND SETTINGS The flexib le TDM m ode used on the SDATA_IN[1:0] serial input port s can als sed on the SDA output p o rts. There utpu t channels available to the output p orts in flexi ble de. ...
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... Figure 58. Flexible TDM Inte rface Mode —Output Routing Example rs (Address 0x E1C0 to Address 0xE1DF) des R egisters d TDM Slot 29 (SDATA_OUT0) 1 Rev Page ADAU1442/ADAU1445/ADAU1446 ...
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... ADAU1442/ADAU1445/ADAU1446 Address Name Decimal Hex 57821 E1DD TDM Slot 58 and TDM Slot 59 (SDATA_OUT1) 57822 E1DE TDM Slot 60 and TDM Slot 61 (SDATA_OUT1) 57823 E1DF TDM Slot 62 and TDM Slot 63 (SDATA_OUT1) 1 Slot 31 and Slot 63 can only be used to hold the MS byte of an 8-bit channel and cannot be used in conjunction with other slots to hold more than eight bits of data. ...
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... Figure 59 shows an example of a dress increments wave. ason for the target s is calculated relative to ddress 0x000A, the written. Rev Page ADAU1442/ADAU1445/ADAU1446 ne. This address als o serves as t afeload write is tri ggered on the next frame. nism is software ba sed and executes once udio frame. Ther ...
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... ADAU1442/ADAU1445/ADAU1446 GLOBAL RAM AND REGI STER MAP This section contains a list RAMS and registers. OVERVIEW OF REGISTER ADDRESS MAP Table 82. ADAU1442/ADAU1445/ADAU1446 RAM and Reg Address Decimal Start Value End Value Start Value 0 4095 0000 8192 12287 2000 16384 24575 4000 5 7344 ...
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... Pair 0 (Channel 0, Channel 1) (Chann el 10, Channel 11) (Channel 12 , Channel 13) Rev Page ADAU1442/ADAU1445/ADAU1446 Read/Write Word Length 16 bits (2 bytes) 16 bits (2 bytes) 16 bits (2 bytes) 16 bits (2 bytes) 16 bits (2 by tes) 16 bits (2 by tes) 16 bits (2 by tes) 16 bits (2 by tes) ...
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... ADAU1442/ADAU1445/ADAU1446 Address Name Decimal Hex 57491 E093 S erial outpu 57492 E094 S erial outpu 57493 E095 S erial outpu 57494 E096 S erial outpu 57495 E097 S erial outpu 57496 E098 S erial outpu 57497 E099 S erial outpu 57498 E09A Se rial outpu 57499 E09B S erial outpu Table 89 ...
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... TDM Slot 52 and TDM Slot 53 (SDATA_OUT1) 57819 E1DB TDM Slot 54 and TDM Slot 55 (SDATA_OUT1) 57820 E1DC TDM Slot 56 and TDM Slot 57 (SDATA_OUT1) d TDM Slot 21 (SDATA_OUT0) UT0) UT0) Rev Page ADAU1442/ADAU1445/ADAU1446 Read/Write Word Length 16 b its (2 bytes its (2 bytes its (2 bytes its (2 bytes ...
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... ADAU1442/ADAU1445/ADAU1446 Address Name Decimal Hex 57821 E1DD TDM Slot 58 and TDM Slot 59 (SDATA_OUT1) 57822 E1DE TDM Slot 60 and TDM Slot 61 (SDATA_OUT1) 57823 E1DF TDM Slot 62 and TDM Slot 63 (SDATA_OUT1) Table 93. Other M odes R egiste rs Address Decimal ame 57856 E20 0 C yclic Redundancy Check Ideal Value ...
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... All 100 nF bypass capaci tors, w hich are recommended for every a nalog, digital, and PLL power-ground pair, should be placed as cl ose to the ADAU1442/ADAU1445/ADAU1446 as possible. The AVDD, DVDD, PVDD, and IO VDD supply signals on the board sh ould each b e bypassed ith an additional single bulk w capacitor ( 10 μ ...
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... ADAU1442/ADAU1445/ADAU1446 100nF IOVDD DGND 1 100nF 2 IOVDD IOVDD 13 DGND 100nF 14 IOVDD DVDD DVDD 100nF BULK BYPASS CAPACITORS D3V3 AVDD PVDD IOVDD DVDD + + + + 10μF 10μF 10μF 10μF DVD D IOVDD 100nF 100nF ADA U1442/ADA ...
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... DVDD 10kΩ 100nF 100nF DVDD DVDD IOVDD DVDD SELF-BOOT 1kΩ SWITCH + + 10μF 10μF D3V3 Figure 64. Self-Boot Application Schematic Rev Page ADAU1442/ADAU1445/ADAU1446 IOVDD DVDD 100nF 100nF DVDD BCLK8 SDATA_IN8 SDATA_OUT5 LRCLK9 BCLK9 SDATA_OUT6 LRCLK10 BCLK10 SDATA_OUT7 LRCLK11 BCLK11 IOVDD DGND ...
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... BULK BYPASS CAPACITORS D3V3 AVDD PVDD IOVDD DVDD + + + + 10μF 10μF 10μF DVDD IOVDD 100nF 100nF ADAU1442/ADAU1445/ADAU1446 10kΩ 100nF 100nF 100nF DVDD IOVDD IOVDD 10μF 1kΩ D3V3 REGULATOR 2 Figure 65 Control Application Schematic Rev Page IOVDD DVDD 100nF 100nF ...
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... AVDD PVDD IOVDD DVDD + + + + 10μF 10μF 10μF 10μF Figure 66. SPI Control Application Schematic ADAU1442/ADAU1445/ADAU1446 IOVDD DVDD 100nF 100nF ADAU1442/ADAU1445/ADAU1446 AVDD 10kΩ 100nF 100nF 100nF DVDD IOVDD PVDD DVDD 1kΩ 22pF 22pF SELF-BOOT SWITCH DVDD 1kΩ D3V3 REGULATOR Rev Page ...
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... TQFP_EP 100-Lead TQFP_EP, 13” Tape and Reel 100-Lead TQFP_EP 100-Lead TQFP_EP, 13” Tape and Reel 100-Lead LQFP 100-Lead LQFP, 13” Tape and Reel Evaluation Board Used for the ADAU1442/ADAU1445 ADAU1446 Evaluation Board 2 C Standard Specification as defined by Philips. D07696-0-9/10(C) Rev Page ...