S1D13700F01A100 Epson, S1D13700F01A100 Datasheet - Page 79

• Manufacturer Part Number: S1D13700F01A100
• Description: Display Drivers LCD CONTROLLER
• Manufacturer: Epson

Specifications of S1D13700F01A100

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

13: POWER SAVE MODES
13.4 Panel Power Up/Down Sequence
13.5 Turning Off BCLK Between Accesses
1-70
Hardware Power Save
Software Power Save
(except LCDPWR)
After chip reset or when entering/exiting a power save mode, the Panel Interface signals follow a
power on/off sequence shown below. This sequence is essential to prevent damage to the LCD panel.
After chip reset, LCDPWR is inactive and the rest of the panel interface output signals are held
“low”. Software initializes the chip (i.e. programs all registers except the Look-Up Table registers)
and then programs REG[03h] bits [1:0] to 11b. This starts the power-up sequence as shown. The
power-up/power-down sequence delay is 127 frames. The Look-Up Table registers may be
programmed any time after REG[03h] bits[1:0] = 11b.
The power-up/power-down sequence also occurs when exiting/entering Software Power Save Mode.
BCLK may be turned off (held low) between accesses if the following rules are observed:
1. BCLK must be turned off/on in a glitch free manner
2. BCLK must continue for a period equal to [8T
3. BCLK must be present for at least one T
Panel Interface
Output Signals
REG[03h] bits [1:0]
(RDY# asserted or WAIT# deasserted).
or
LCDPWR
RESET#
00
power-up
0 frame
Figure 13-1 Panel On/Off Sequence
11
EPSON
BCLK
before the start of an access.
BCLK
127 frames
power-down
+ 12T
Power Save Mode
MCLK
S1D13705F00A HARDWARE FUNCTIONAL
00
] after the end of the access
SPECIFICATION (X27A-A-001-06)
power-up
0 frame
11