S1D13700F01A100 Epson, S1D13700F01A100 Datasheet - Page 112

• Manufacturer Part Number: S1D13700F01A100
• Description: Display Drivers LCD CONTROLLER
• Manufacturer: Epson

Specifications of S1D13700F01A100

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

7.4 Registers
S1D13705F00A PROGRAMMING NOTES
AND EXAMPLES (X27A-G-002-01)
REG[0Ch] Screen 1 Start Word Address LSB
REG[0Dh] Screen 1 Start Word Address MSB
REG[0Eh] Screen 1 Start Word Address MSB
REG[1Ch] Line Byte Count Register
REG[1Bh] SwivelView Mode Register
Mode Enable
SwivelView
bit 15
bit 7
bit 7
n/a
This section describes the registers used to set SwivelView mode operation.
The Screen 1 Start Address registers must be set correctly for SwivelView mode. In SwivelView
mode the Start Address registers form a byte offset, as opposed to a word offset, into display
memory.
The initial required offset is the SwivelView mode stride (in bytes) less one.
The line byte count register informs the S1D13705 of the stride, in bytes, between two consecutive
lines of display in SwivelView mode. The Line Byte Count register only affects SwivelView mode
operation and are ignored when the S1D13705 is in landscape display mode.
The SwivelView mode register contains several items for SwivelView mode support.
The first is the SwivelView Mode Enable bit. When this bit is “0” the S1D13705 is in landscape
mode and the remainder of the settings in this register as well as the Line Byte Count in REG[1Ch]
are ignored. Set this bit to “1” to enable SwivelView mode.
The SwivelView mode select bit selects between the “Default Mode” and the “Alternate Mode”.
Setting this bit to “0” selects the default SwivelView mode while setting this bit to “1” enables the
alternate SwivelView mode.
SwivelView Mode Memory Clock Select is another power saving measure which can be enabled if
the final MCLK value is less than or equal to 25 MHz. Memory Clock Select results in the
S1D13705 temporarily increasing the memory clock circuitry on CPU access and resuming the
slower speed when the access is complete. This results in better performance while using the least
power.
In SwivelView display mode the CLKI (input clock) is routed to the SwivelView section of the
S1D13705 as CLK. From the CLK signal the MCLK value can be determined from table 8-8 of the
Hardware Functional Specification, document number X27A-A-001-xx. If MCLK is determined to
be less than or equal to 25 MHz then SwivelView Mode Memory Clock Select may be enabled.
Mode Select
SwivelView
bit 14
bit 6
bit 6
n/a
bit 13
n/a
bit 5
bit 5
n/a
n/a
bit 12
bit 4
bit 4
n/a
EPSON
n/a
bit 11
bit 3
bit 3
n/a
Mode Memory
Clock Select
SwivelView
bit 10
bit 2
bit 2
n/a
Mode Pixel Clock
SwivelView
Select Bit 1
7: HARDWARE ROTATION
bit 1
bit 9
bit 1
n/a
Mode Pixel Clock
SwivelView
Select Bit 0
bit 16
bit 0
bit 8
bit 0
2-27