S1D13700F01A100 Epson, S1D13700F01A100 Datasheet - Page 190

• Manufacturer Part Number: S1D13700F01A100
• Description: Display Drivers LCD CONTROLLER
• Manufacturer: Epson

Specifications of S1D13700F01A100

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

6: TECHNICAL DESCRIPTION
6.9 Color TFT/D-TFD LCD Panel Support
6.10 Power Save Modes
6.11 Adjustable LCD Panel Negative Power Supply
6.12 Adjustable LCD Panel Positive Power Supply
6.13 CPU/Bus Interface Header Strips
4-10
The S1D13705 directly supports 9 and 12-bit active matrix color TFT/D-TFD panels. All the
necessary signals can also be found on the 40-pin LCD connector J5. The interface signals on the
cable are alternated with grounds to reduce crosstalk and noise.
Refer to “Table 3-1 LCD Signal Connector (J5) Pinout,” on page 4-3 for connection information.
The S1D13705 supports hardware and software power save modes. These modes are controlled by
the utility 1375PWR. The hardware power save mode needs to be enabled by 1375PWR and then
activated by DIP switch S1-6. See “Table 2-1 Configuration DIP Switch Settings,” on page 4-2 for
details on setting this switch.
For those LCD panels requiring a negative power supply to provide between -23V and -14V
(I
supply can be adjusted by R21 to give an output voltage from -23V to -14V, and is enabled and
disabled by the active high S1D13705 control signal LCDPWR, inverted externally.
Determine the panel’s specific power requirements and set the potentiometer accordingly before
connecting the panel.
For those LCD panels requiring a positive power supply to provide between +23V and +40V
(I
supply can be adjusted by R15 to provide an output voltage from +23V to +40V and is enabled and
disabled by the active high S1D13705 control signal LCDPWR, inverted externally.
Determine the panel’s specific power requirements and set the potentiometer accordingly before
connecting the panel.
All of the CPU/Bus interface pins of the S1D13705 are connected to the header strips H1 and H2 for
easy interface to a CPU/Bus other than ISA.
Refer to “Table 4-1 CPU/BUS Connector (H1) Pinout,” on page 4-4 and “Table 4-2 CPU/BUS
Connector (H2) Pinout,” on page 4-5 for specific settings.
Note: These headers only provide the CPU/bus interface signals from the S1D13705. When another
out
out
=25mA) a power supply has been provided as an integral part of this design. The VLCD power
=45mA) a power supply has been provided as an integral part of this design. The VDDH power
host bus interface is selected by CNF[3:0] and BS#, appropriate external decoding logic MUST
be used to access the S1D13705. Refer to “Table 5-1 Host Bus Interface Pin Mapping,” on
page 4-6 for connection details.
EPSON
S5U13705B00C REV. 1.0 ISA BUS EVALUATION
BOARD USER’S MANUAL (X27A-G-005-01)