S1D13700F01A100 Epson, S1D13700F01A100 Datasheet - Page 152

• Manufacturer Part Number: S1D13700F01A100
• Description: Display Drivers LCD CONTROLLER
• Manufacturer: Epson

Specifications of S1D13700F01A100

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Miscellaneous Options
S1D13705F00A UTILITIES (X27A-B-001-01)
Miscellaneous options cover several items which do not fit into other categories.
• HW Video Invert Enable - when selected, enables the hardware video invert capability
• HW Power Save Enable - select this option to enable hardware invoked power save
• High Performance - improves chip throughput at the expense of power consumption.
• SwivelView Mode - selecting this option causes register settings and timings to be saved for
The S1D13705 supports inverted color output. The color inversion can be toggled by software or
in response to a signal applied to pin FPDAT11. In order for the hardware color inversion to
succeed this option must be selected, or the software must enable this feature at run time.
There are two methods of performing color inversion. In the first scheme the display memory
data is inverted and the resulting color is derived from the corresponding Look-Up Table
element. (i.e. the inverse of color 0 would be whatever color was LUT[FF] was set to. If element
0 and FF were both set to set to White then we would observe the inverse of white as being
white). The second scheme is to invert the data as it comes out of the Look-Up Table resulting in
a true color inversion. The S1D13705 uses the second method.
TFT panels require all the FPDAT control lines, as a result hardware color inversion is not
possible when using TFT panels. Software invoked color inversion can be invoked when using
TFT panels.
The S1D13705 supports two means of invoking a power save mode. In response to a software
effected change or in response to input on the GPIO0 pin. In order for the hardware power save
mode to function this option must be selected.
When not selected the memory clock (MCLK) signal is a divided down version of the pixel
clock (PCLK) signal. Table 1 depicts the ratios when high performance is not selected.
With slower MCLK selections comes lower performance and also lower power use. This setting
allows the user to trade off power consumption for system performance.
Selecting this option result in MCLK equalling PCLK at all display resolution. Overall
performance is increased but so is power consumption.
SwivelView mode operation.
Color Depth (bpp)
Figure 1-3 Miscellaneous Options
of the S1D13705.
modes.
Table 1-1 MCLK to PCLK Ratios
1
2
4
8
EPSON
MCLK = PCLK / 8
MCLK = PCLK / 4
MCLK = PCLK / 2
MCLK = PCLK
Ratio
1: 1375CFG CONFIGURATION PROGRAM
3-5