S1D13700F01A100 Epson, S1D13700F01A100 Datasheet - Page 58

• Manufacturer Part Number: S1D13700F01A100
• Description: Display Drivers LCD CONTROLLER
• Manufacturer: Epson

Specifications of S1D13700F01A100

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TQFP
• Pin Count: 80
• Mounting: Surface Mount
• Operating Supply Voltage (min): 2.7V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

S1D13705F00A HARDWARE FUNCTIONAL
SPECIFICATION (X27A-A-001-06)
REG[09h] FPFRAME Start Position
Address = 1FFE9h
REG[0Ah] Vertical Non-Display Period
Address = 1FFEAh
REG[0Bh] MOD Rate Register
Address = 1FFEBh
Display Status
Vertical Non-
n/a
n/a
bits 5-0
bit 7
bits 5-0
Note: This register should be set only once, on power-up during initialization.
bits 5-0
FPFRAME Start Position
These bits are used in TFT/D-TFD mode to specify the position of the FPFRAME pulse.
These bits specify the number of lines between the last line of display data (FPDAT) and
the leading edge of FPFRAME. This register is effective in TFT/D-TFD mode only
(REG[01h] bit 7 = 1). This register is programmed as follows:
The contents of this register must be greater than zero and less than or equal to the Verti-
cal Non-Display Period Register, i.e.
Vertical Non-Display Status
This bit =1 during the Vertical Non-Display period.
Vertical Non-Display Period
These bits specify the vertical non-display period. This register is programmed as fol-
lows:
MOD Rate Bits [5:0]
When the value of this register is 0, the MOD output signal toggles every FPFRAME. For
a non-zero value, the value in this register + 1 specifies the number of FPLINEs between
toggles of the MOD output signal. These bits are for passive LCD panels only.
n/a
n/a
n/a
Vertical Non-Display Period (lines)
Display Period
Start Position
Vertical Non-
FPFRAME
MOD Rate
FPFRAMEposition lines
Bit 5
Bit 5
Bit 5
1 REG 09h
Display Period
Start Position
Vertical Non-
FPFRAME
MOD Rate
Bit 4
Bit 4
Bit 4
EPSON
REG 0Ah
Display Period
Start Position
Vertical Non-
FPFRAME
MOD Rate
=
=
Bit 3
Bit 3
Bit 3
REG 09h
REG[0Ah] bits [5:0]
Display Period
Start Position
Vertical Non-
FPFRAME
MOD Rate
Bit 2
Bit 2
Bit 2
Display Period
Start Position
Vertical Non-
FPFRAME
MOD Rate
Bit 1
Bit 1
Bit 1
8: REGISTERS
Display Period
Start Position
Vertical Non-
FPFRAME
MOD Rate
Read/Write
Read/Write
Read/Write
Bit 0
Bit 0
Bit 0
1-49